cpu: allow the fetch buffer to be smaller than a cache line

Information
Submitter:	Tony Gutierrez
Repository:	gem5
Branch:	default
Bugs:
Depends On:
Reviewers
Groups:	Default
People:

Description

Changeset 9821:9e2898b0e9bd
---------------------------
cpu: allow the fetch buffer to be smaller than a cache line

the current implementation of the fetch buffer in the o3 cpu
is only allowed to be the size of a cache line. some
architectures, e.g., ARM, have fetch buffers smaller than a cache
line, see slide 22 at:
http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

this patch allows the fetch buffer to be set to values smaller
than a cache line.

Testing Done

ran several of the shorter SPEC CPU2006 benchmarks with test input.
icache.overall_accesses::total stat was validated against real
cortex A15 hardware, the value is much closer now.

regressions pass

Issue Summary

Description	From	Last Updated	Status
(bytes) at the end of the comment would be great	Andreas Hansson	Feb. 18, 2013, 1:40 a.m.	Resolved
Would fetchBufferOffset not be a better description? Perhaps I'm misunderstanding the use...but the word Index doesn't seem to describe what ...	Andreas Hansson	Feb. 18, 2013, 1:40 a.m.	Resolved
warn or even fatal?	Andreas Hansson	Feb. 18, 2013, 1:40 a.m.	Resolved
Comments please	Andreas Hansson	Feb. 18, 2013, 1:41 a.m.	Resolved

Description:

		Changeset 9543:79bf565a7f7a

~		O3 CPU: add an option to set the fetch buffer size
	~	O3 CPU: allow the fetch buffer to be smaller than a cache line

		the current implementation of the fetch buffer in the o3 cpu
		is only allowed to be the size of a cache line. some
		architectures, e.g., ARM, have fetch buffers smaller than a cache
		line, see slide 22 at:
		http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

		this patch allows the fetch buffer to be set to values smaller
		than a cache line.

Summary:

-	O3 CPU: add an option to set the fetch buffer size
+	O3 CPU: allow the fetch buffer to be smaller than a cache line

Testing Done:

	+	ran several of the shorter SPEC CPU2006 benchmarks with test input.
	+	icache.overall_accesses::total stat was validated against real
	+	cortex A15 hardware, the value is much closer now.

src/cpu/o3/O3CPU.py (Diff revision 1)

(bytes) at the end of the comment would be great

Show all issues

src/cpu/o3/fetch.hh (Diff revision 1)

Would fetchBufferOffset not be a better description? Perhaps I'm misunderstanding the use...but the word Index doesn't seem to describe what is done.

Show all issues

src/cpu/o3/fetch_impl.hh (Diff revision 1)

warn or even fatal?

Show all issues

Tony Gutierrez Feb. 18, 2013, 1:41 a.m. (Feb. 18, 2013, 1:41 a.m.)

Chose fatal. Don't want this to run if the users have certain assumptions that aren't true, without them knowing.

src/cpu/o3/fetch_impl.hh (Diff revision 1)

Comments please

Show all issues

Summary:

-	O3 CPU: allow the fetch buffer to be smaller than a cache line
+	O3 CPU: add an option to set the fetch buffer size

Description:

~		Changeset 9543:79bf565a7f7a
	~	Changeset 9543:35442b688954

~		O3 CPU: allow the fetch buffer to be smaller than a cache line
	~	O3 CPU: add an option to set the fetch buffer size

		the current implementation of the fetch buffer in the o3 cpu
		is only allowed to be the size of a cache line. some
		architectures, e.g., ARM, have fetch buffers smaller than a cache
		line, see slide 22 at:
		http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

		this patch allows the fetch buffer to be set to values smaller
		than a cache line.

Diff:

Revision 2 (+38)

Show changes

	configs/common/O3_ARM_v7a.py
	src/cpu/o3/O3CPU.py
	src/cpu/o3/fetch.hh
	src/cpu/o3/fetch_impl.hh

Summary:

-	O3 CPU: add an option to set the fetch buffer size
+	O3 CPU: allow the fetch buffer to be smaller than a cache line

Description:

~		Changeset 9543:35442b688954
	~	Changeset 9543:8e8b5807a84d

~		O3 CPU: add an option to set the fetch buffer size
	~	O3 CPU: allow the fetch buffer to be smaller than a cache line

		the current implementation of the fetch buffer in the o3 cpu
		is only allowed to be the size of a cache line. some
		architectures, e.g., ARM, have fetch buffers smaller than a cache
		line, see slide 22 at:
		http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

		this patch allows the fetch buffer to be set to values smaller
		than a cache line.

Diff:

Revision 3 (+38)

Show changes

	configs/common/O3_ARM_v7a.py
	src/cpu/o3/O3CPU.py
	src/cpu/o3/fetch.hh
	src/cpu/o3/fetch_impl.hh

LGTM. Nice job...on President's day and all :-)

Description:

~		Changeset 9543:8e8b5807a84d
	~	Changeset 9543:d67d38fdc178

		O3 CPU: allow the fetch buffer to be smaller than a cache line

		the current implementation of the fetch buffer in the o3 cpu
		is only allowed to be the size of a cache line. some
		architectures, e.g., ARM, have fetch buffers smaller than a cache
		line, see slide 22 at:
		http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

		this patch allows the fetch buffer to be set to values smaller
		than a cache line.

Diff:

Revision 4 (+41)

Show changes

	configs/common/O3_ARM_v7a.py
	src/cpu/o3/O3CPU.py
	src/cpu/o3/fetch.hh
	src/cpu/o3/fetch_impl.hh

this seems fine with me. If you set the buffer size to 64, do you see any statistics changes? If not, feel free to commit.

Tony Gutierrez Feb. 26, 2013, 11:29 p.m. (Feb. 26, 2013, 11:29 p.m.)

There are a few more misses, not a significant number, but there are more. I'm still trying to figure out why.

Ali Saidi July 15, 2013, 8:24 a.m. (July 15, 2013, 8:24 a.m.)
```
Any updates? Should we get this committed?
```

Tony Gutierrez Aug. 13, 2013, 2:19 p.m. (Aug. 13, 2013, 2:19 p.m.)

Took a different approach and just turned cacheData into an actual fetch buffer. When set to 64B this change makes no difference over the previous code. Setting to 16B in ARM makes it closer to results observed in HW. Regressions pass.

Summary:

-	O3 CPU: allow the fetch buffer to be smaller than a cache line
+	cpu: allow the fetch buffer to be smaller than a cache line

Description:

~		Changeset 9543:d67d38fdc178
	~	Changeset 9821:9e2898b0e9bd

~		O3 CPU: allow the fetch buffer to be smaller than a cache line
	~	cpu: allow the fetch buffer to be smaller than a cache line

		the current implementation of the fetch buffer in the o3 cpu
		is only allowed to be the size of a cache line. some
		architectures, e.g., ARM, have fetch buffers smaller than a cache
		line, see slide 22 at:
		http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

		this patch allows the fetch buffer to be set to values smaller
		than a cache line.

Diff:

Revision 5 (+73 -50)

Show changes

	configs/common/O3_ARM_v7a.py
	src/SConscript
	src/cpu/o3/O3CPU.py
	src/cpu/o3/fetch.hh
	src/cpu/o3/fetch_impl.hh

Testing Done:

		ran several of the shorter SPEC CPU2006 benchmarks with test input.
		icache.overall_accesses::total stat was validated against real
		cortex A15 hardware, the value is much closer now.
	+
	+	regressions pass

LTGM! Thanks!

I'm planning on shipping this today, unless someone has an objection.

I'm planning on shipping this today, unless someone has an objection.

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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Issue Summary

Description:

Changeset 9543:79bf565a7f7a

Summary:

Testing Done:

Summary:

Description:

Changeset 9543:79bf565a7f7a

Changeset 9543:35442b688954

Diff:

Summary:

Description:

Changeset 9543:35442b688954

Changeset 9543:8e8b5807a84d

Diff:

Description:

Changeset 9543:8e8b5807a84d

Changeset 9543:d67d38fdc178

Diff:

Summary:

Description:

Changeset 9543:d67d38fdc178

Changeset 9821:9e2898b0e9bd

Diff:

Testing Done:

Status: Closed (submitted)