Changeset 9571:cda786f0fb05
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cache: Fix issue where IO cache read, prefetch and dirty data in L1 cause coherence bug.

This change fixes an issue with a IO device reading a block that the is dirty
in an L1 and a prefetch from a l2 collide to produce a coherency issue. In this case the prefetch is
pending in the L2 just as the IO cache requests the line, beacuse the state is
in the MSHR the L2 believes it's getting a copy, but doesn't know the copy is
dirty, so it doesn't assert mem inhibit, which causes DRAM to respond, and then
the L1 sees the snoop and tries to respond.