Changeset 9818:438f37f51ba2
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mem: model data array bank in classic cache
The classic cache does not model data array bank, i.e. if a read/write is being
serviced by a cache bank, no other requests should be sent to this bank.
This patch models a multi-bank cache.  Features include:
1. detect if the bank interleave granularity is larger than cache line size
2. add CacheBank debug flag
3. Differentiate read and write latency
3a. read latency is named as read_latency
3b. write latency is named as write_latency
4. Add write_latency, num_banks, bank_itlv_bit into the Python parser
5. Enabling bank model by --l1-bank-model, --l2-bank-model, --l3-bank-model
Not modeled in this patch:
Due to the lack of retry mechanism in the cache master port, the access form
the memory side will not be denied if the bank is in service. Instead, the bank
service time will be extended. This is equivalent to an infinite write buffer
for cache fill operations.