Review Board 2.0.15


ARM: Make sure that software prefetch instructions can't change the state of the TLB

Review Request #192 - Created Aug. 13, 2010 and submitted

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Ali Saidi
gem5
Reviewers
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ARM: Make sure that software prefetch instructions can't change the state of the TLB

   
Posted (Aug. 13, 2010, 5:33 p.m.)



  
src/mem/cache/cache_impl.hh (Diff revision 1)
 
 
Don't comment out code, delete it. Why is this assert no longer needed? I don't know the cache code so I apologize if it's obvious.
  1. This assertion checks that you don't have an uncacheable access to a block that's already in your cache, since there's no well-defined general behavior for that.  I don't see how it's related to the stated goal of this patch, and I don't want to see it removed without some discussion about why it's wrong.
    
Posted (Aug. 14, 2010, 12:35 a.m.)
Is this really desired behavior?  Aren't there cases when having a software prefetch prefetching results into the TLB is a good idea?  To be honest I don't know what our processors do; I'll try and find out.
Posted (Aug. 17, 2010, 8:37 a.m.)



  
src/mem/cache/cache_impl.hh (Diff revision 1)
 
 
It's possible to be using the caches for a region of memory and then mark in uncachable with ARM. In this case we'l step on this assert. The above change causes the cache to invalidate that block when this happens. 
Posted (Aug. 19, 2010, 3:34 a.m.)



  
src/arch/arm/faults.hh (Diff revision 1)
 
 
Space after // in comments.  I know it's not explicitly stated in the style guide, but the examples are consistent and it is what almost all other code does.  We could update the style guide of course.

In the future, to make life easier, I wouldn't mind having the rule that we follow the Google style guide when our style guide is silent.  (I don't know the guide myself, but my guess is that it's decent).
  1. fixed.