This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. 
Instead of bytesPerCacheLine, I define a parameter for DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits.
Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve code portablity.

Updates: 
- a burst length in beats for each memory type.
- an interface width for each memory type.
- the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets.

Some short and fairly long tests on DDR3 and LPDRR3 with cache lines of 32, 64, and 128 bytes.