x86: Implementation of Int3 and Int_Ib in long mode

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Submitter:	Christian Menard
Repository:	gem5
Branch:	default
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Description

This is an implementation of the x86 int3 and int immediate instructions for long mode according to 'AMD64 Programmers Manual Volume 3'. I did not do any heavy testing, but it works fine with the Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/). I'm not sure if the changes to the decoder (one_byte_opcodes.isa) break the way Linux-syscalls are currently treated. So please have a look at it.

Testing Done

Test runs with Fiasco.OC micro kernel (http://os.inf.tu-dresden.de/fiasco/)

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Revision 2 (+219 -19)

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	src/arch/x86/isa/decoder/one_byte_opcodes.isa
	src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

I do not like that form WarnUnimpl being repeated all over the place.
Can you try if something else works?

Ali Saidi Aug. 27, 2013, 6:21 p.m. (Aug. 27, 2013, 6:21 p.m.)

I'm afraid that is somewhat like how the isa description language works. Perhaps the unimplemented case could be the default and overwritten else where, but i don't think it's going to improve the situation much.

Steve Reinhardt Aug. 27, 2013, 7:54 p.m. (Aug. 27, 2013, 7:54 p.m.)

On closer inspection, all the 'format WarnUnimpl' clauses are unnecessary.  The old code was just setting the default format to WarnUnimpl, then overriding it in some cases with the Inst:: prefix (which is the default format outside of the 'format WarnUnimpl' block).  So it's totally equivalent to get rid of the 'format WarnUnimpl' block, delete all the 'Inst::' prefixes, and add 'WarnUnimpl::' to the few unprefixed instruction declarations.  I tried it, and it seems to work... I can't update this patch, but I'll upload another one.

That said, I'm a little mystified how this code still works since the 'xc->syscall()' call seems to be missing entirely now.

Change Summary:

After my question on the mailing list I updated this patch. The instructions now just check if the CPU runs in long or in legacy mode and jumps to the corresponding rom labels. The Decoder was changed as well. Now should be able to handle linux syscalls (int 80) in SE mode as well as soft interrupts in FS mode.

Diff:

Revision 3 (+33 -2)

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	src/arch/x86/isa/decoder/one_byte_opcodes.isa
	src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

It seems like the diff doesn't apply cleanly in RB. It happens from time to time, it's kinda crap.

I think you probably don't want to add the 'default: Inst::INT(Ib);' to the SE-mode case, just using 'Inst::INT(Ib)' as the default when FullSystemInt != 0 should suffice. I'd be very surprised if taking an interrupt in SE mode is going to do anything sensible.

I think you should be able to do 'limm t1, imm, dataSize=8' instead of clearing t1 first.

Also, are you sure the long mode test is correct? Isn't it supposed to be something like this:
andi t0, t5, 0x1, flags=(EZF,)
br rom_label("longModeSoftInterrupt"), flags=(nCEZF,)

IIRC, the least significant bit of the handy m5 reg is 0 for long mode and 1 for the the legacy modes.

Christian Menard Oct. 22, 2013, 1:14 a.m. (Oct. 22, 2013, 1:14 a.m.)

You are right about 'default: Inst::INT(Ib);', I just put it into the wrong block.

I thought about using 'limm t1, imm, dataSize=8' too. But I'm not sure how the byte sized immediate is treated. I think it will be sign extended this way.

The long mode test is correct. It does not check the IIRC but the 3 bits left of it. They represent the submode, in 64-bit mode these bits are 0. But just checking the least significant bit should do the same trick. But in the 'br' instruction ypu have to check for the 'CEZF', because the result of the 'andi' is 0 in long mode.

Change Summary:

Fixed the 'default: Inst::INT(Ib)'.

Diff:

Revision 4 (+33 -2)

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	src/arch/x86/isa/decoder/one_byte_opcodes.isa
	src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

Change Summary:

Changed the isa description of INT(Ib) and INT3 as suggested by Andreas.

Thanks for your help and support.

Diff:

Revision 5 (+33 -2)

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	src/arch/x86/isa/decoder/one_byte_opcodes.isa
	src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

Looks good! Thanks!

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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Status: Closed (submitted)