Extends the classic prefetcher.

This patch, originally started by Amin Farmahini, extends the classic prefetcher to work on non-block aligned addresses.  Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected.  For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern.  This patch fixes this, by training the prefetcher on access and not masking off the lower address bits.

It also adds the following configuration options:  1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address.  #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers
present at multiple levels.  It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy.

Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7%  for SPECFP (geomean).

Benchmarked SPEC2006 simpoints, will post on the dev mailing list with more detailed results.