kvm: x86: Fix segment registers to make them VMX compatible

Information
Submitter:	Andreas Sandberg
Repository:	gem5
Branch:	default
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Description

Changeset 9884:5032bc7bffb9
---------------------------
kvm: x86: Fix segment registers to make them VMX compatible

There are cases when the segment registers in gem5 are not compatible
with VMX. This changeset works around all known such issues. Specifically:

* The accessed bits in CS, SS, DD, ES, FS, GS are forced to 1.
* The busy bit in TR is forced to 1.
* The protection level of SS is forced to the same protection level as
  CS. The difference /seems/ to be caused by a bug in gem5's x86
  implementation.

Testing Done

Issue Summary

Description	From	Last Updated	Status
Just noticed a typo in "synchronization" here.	Steve Reinhardt	Sept. 30, 2013, 12:36 a.m.	Resolved

src/cpu/kvm/x86_cpu.cc (Diff revision 1)

It may be needed for a hack, but I think 'forceSegAccessed' or 'markSegAccessed' would be better names

Andreas Sandberg Sept. 19, 2013, 2:01 a.m. (Sept. 19, 2013, 2:01 a.m.)
```
Renamed to forceSegAccessed.
```

src/cpu/kvm/x86_cpu.cc (Diff revision 1)

Is this a long-term issue, or is this something that should get fixed (e.g., if our x86 CPU model set these bits properly)?  If the former, I'd say there's no need for this message...

Andreas Sandberg Sept. 19, 2013, 2:01 a.m. (Sept. 19, 2013, 2:01 a.m.)

After reading more about how the accessed bit is used on x86, this seems to be a VMX limitation rather than a CPU model bug. I'll remove the warning.

src/cpu/kvm/x86_cpu.cc (Diff revision 1)

Do we have an enum or some typedefs somewhere for these type codes?  It would be nice to avoid these hardwired constants.

Andreas Sandberg Sept. 19, 2013, 2:01 a.m. (Sept. 19, 2013, 2:01 a.m.)

We have unions defined for whole segment descriptors, but not for the type field separately. I'll make these into separate defines (similar to some of the IO addresses we need in the KVM CPU). I think that's a better solution than breaking out the type subunion from the SegDescriptor bitunion since they are referred to by number in the VMX documentation.

src/cpu/kvm/x86_cpu.cc (Diff revision 1)

Looks like some spurious whitespace got added here

Andreas Sandberg Sept. 19, 2013, 2:01 a.m. (Sept. 19, 2013, 2:01 a.m.)
```
Fixed.
```

Description:

~		Changeset 9873:45f1f3674815
	~	Changeset 9884:5032bc7bffb9

		kvm: x86: Fix segment registers to make them VMX compatible

		There are cases when the segment registers in gem5 are not compatible
		with VMX. This changeset works around all known such issues. Specifically:

		The accessed bits in CS, SS, DD, ES, FS, GS are forced to 1.
		The busy bit in TR is forced to 1.
		The protection level of SS is forced to the same protection level as CS. The difference /seems/ to be caused by a bug in gem5's x86 implementation.
-
-
-
-		This patch is a part of series of changes to add support for KVM on x86. See https://github.com/andysan/gem5/tree/kvm-x86 for the full series.

Diff:

Revision 2 (+59)

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src/cpu/kvm/x86_cpu.cc

Ship It!

src/cpu/kvm/x86_cpu.cc (Diff revisions 1 - 2)

Just noticed a typo in "synchronization" here.

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Issue Summary

Description:

Changeset 9873:45f1f3674815

Changeset 9884:5032bc7bffb9

Diff:

Status: Closed (submitted)