mem: Add tRAS parameter to the DRAM controller model
Review Request #2043 - Created Oct. 16, 2013 and submitted - Latest diff uploaded
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 9914:0ebbd47c9444 --------------------------- mem: Add tRAS parameter to the DRAM controller model This patch adds an explicit tRAS parameter to the DRAM controller model. Previously tRAS was, rather conservatively, assumed to be tRCD + tCL + tRP. The default values for tRAS are chosen to match the previous behaviour and will be updated later.
All regressions pass