cpu: `Minor' in-order CPU model
Review Request #2279 - Created May 30, 2014 and submitted
| Information | |
|---|---|
| Ali Saidi | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Minor is faster than the o3 model. Sample results:
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Boots Linux and runs regression tests for ALPHA and ARM.
Posted (June 4, 2014, 1:15 p.m.)
Nice! I didn't have time to read all the code closely, but I did notice a few things, and wanted to give feedback before I forgot. Basically the comments boil down to three things: 1. There are several pieces (Named, TickedModule, maybe the Expr stuff) that look more broadly useful, and it would be nice not to bury them inside of the CPU model 2. The report() functionality, at least, looks similar to methods on other objects like dump() and print(); we might want to standardize on this 3. A few minor (no pun intended) places where there are formatting inconsistencies with undocumented gem5 conventions As far as #3, I'd be glad to update the coding style page appropriately if people agree that the things I've called out below should be standardized. Where does the name come from? Will you be committing a 'Major' model in the future?
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src/cpu/minor/Expr.py (Diff revision 1) -
This is pretty interesting... it would be nice to generalize this capability and not make it Minor-specific
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src/cpu/minor/cpu.hh (Diff revision 1) -
I don't know why, and I know it's not in the style guide, but all the gem5 code I've seen (or written) has the colon at the beginning of the second line, not the end of the first... might as well be consistent
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src/cpu/minor/decode.cc (Diff revision 1) -
another implicit, undocumented consistency thing: continued arg lists get indented to the opening paren, not just four spaces
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src/cpu/minor/dyn_inst.hh (Diff revision 1) -
I'd put a paren at the beginning of this expression, then indent so all the lines start one column past the paren... keeps the assignment '=' from blending in with all the '=='
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src/cpu/minor/scoreboard.cc (Diff revision 1) -
space after for
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src/cpu/minor/scoreboard.cc (Diff revision 1) -
opening brace at end of previous line (here & a few places below)
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src/cpu/minor/ticked.hh (Diff revision 1) -
This seems like it could be useful outside of Minor... perhaps we should put it in src/sim, or even just integrate this functionality with ClockedObject
-
src/cpu/minor/ticked.hh (Diff revision 1) -
We also have various objects that have dump() or print() methods... it would be nice to standardize this
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src/cpu/minor/ticked.hh (Diff revision 1) -
integrating with ClockedObject would eliminate the multiple inheritance... not that MI is totally evil, but it's always better to avoid it when possible
-
src/cpu/minor/trace.hh (Diff revision 1) -
This would be very useful outside of Minor... should go in src/base/trace.hh, IMO
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src/cpu/static_inst.hh (Diff revision 1) -
blank line here would be nice
Posted (July 1, 2014, 7:01 a.m.)
Last chance for comments?
Looks good, thanks for all the changes. One question: in your email you said that Ticked was separate so it could be "added to objects which are already SimObjects/don't want to be SimObjects". I get the latter, but in the former case, is there a reason not to just make those objects derive from TickedObject now?
