Mem: adding architectural page table support for SE mode
Review Request #2319 - Created July 28, 2014 and submitted
| Information | |
|---|---|
| Alexandru Dutu | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10265:d518cde600e0 --------------------------- Mem: adding architectural page table support for SE mode This patch enables the use of page tables that are stored in system memory and respect x86 specification, in SE mode. It defines an architectural page table for x86 as a MultiLevelPageTable class and puts a placeholder class for other ISAs page tables, giving the possibility for future implementation.
Regressions passed.
Posted (Aug. 14, 2014, 2:22 a.m.)
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src/arch/x86/pagetable.hh (Diff revision 1) -
I'd prefer to see this refactored so that the X86 architectural page table inherits from the multi-level page table instead. (See RB2312.) I find it very hard to believe that there is any performance improvement by using templates here.
Thanks for fixing this! This changeset looks good except for the comment above.
Posted (Aug. 14, 2014, 2:29 a.m.)
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src/arch/x86/pagetable.hh (Diff revision 1) -
Add a comment describing what this is.
Review request changed
Updated (Aug. 25, 2014, 2:10 p.m.)
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Revision 2 (+133 -18) |
Ship It!