Changeset 10286:08c7971d5f0a
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mem: Fix address interleaving bug in DRAM controller

This patch fixes a bug in the DRAM controller address decoding. In
cases where the DRAM burst size was smaller than the interleaving
stripe size (e.g. LPDDR3 x32 with a 64 byte cache line) one address
bit effectively got used as a channel bit when it should have been a
low-order column bit.

This patch adds a notion of "columns per stripe", and more clearly
deals with the low-order column bits and high-order column bits. The
patch also relaxes the granularity check such that it is possible to
use interleaving granularities other than the cache line size.

The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as
it is only used in the debug build for now.