configs/ruby/Ruby.py (Diff revision 1)

We might want to tailor how this is done in the future so that you assign the ranges once, to the directories, and then query the directories for their range rather than recomputing it.

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1. Nilay Vaish Sept. 25, 2014, 7:45 a.m. (Sept. 25, 2014, 7:45 a.m.)

   I am letting this code remain as is for the time being.

src/mem/ruby/slicc_interface/AbstractController.hh (Diff revision 1)

Copy paste :-)

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1. Nilay Vaish Sept. 25, 2014, 7:45 a.m. (Sept. 25, 2014, 7:45 a.m.)

   Now you know where I stole the code from.

src/mem/ruby/slicc_interface/AbstractController.hh (Diff revision 1)

Should this really be a vector?

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1. Nilay Vaish Sept. 25, 2014, 7:45 a.m. (Sept. 25, 2014, 7:45 a.m.)

   I think there can be multiple memory controllers attached to a single
   directory controller.  So there will be a vector for ports, one port
   for each memory controller.

src/mem/ruby/slicc_interface/AbstractController.cc (Diff revision 1)

Should we not have one of these for every memory controller? Or am I missing something?

Is there an 1:N mapping of RubyController to memory controllers? If so, I'd even argue to put a NoncoherentXBar in between and let that XBar deal with the interleaving between the "local" controllers/channels.

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1. Nilay Vaish Sept. 25, 2014, 7:45 a.m. (Sept. 25, 2014, 7:45 a.m.)

   Yes, I am assuming that a single directory controller can be attached to multiple
   memory controllers.  In my understanding the directory controller should
   subsume the role that a NoncoherentXBar would play. This really comes down 
   to how actual systems are / can be designed and I may be wrong due to my lack
   of experience.
   

2. Andreas Hansson Sept. 25, 2014, 10:03 a.m. (Sept. 25, 2014, 10:03 a.m.)

   I agree that one directory controller could be connected to a number of DRAM channels/controllers. I think the most elegant solution here is to have a single MasterPort on the directory controller, and then use a NoncoherentXBar to interleave across the channels. This is also consistent with how we do it  in the classic memory system when using more elaborate system topologies (not part of the normal fs.py or se.py).
   
   Perhaps the best way is to proceed with what you have, and make this change in a future patch?

3. Nilay Vaish Sept. 30, 2014, 2:37 p.m. (Sept. 30, 2014, 2:37 p.m.)

   I have made the changes as you suggested.

First of all: awesome effort! Thanks Nilay

I have some questions around the topology that would be good to iron out, but overall this is a massive step in the right direction.

configs/ruby/Ruby.py (Diff revisions 1 - 2)

I may have confused myself here, so let's see if I have gotten this right.

On the highest level, we have a number of memory ranges in the system (system.mem_ranges). These are possibly of different size etc.

Somehow, and this is where I am not sure how it's done, we interleave these ranges across the directory controllers. Is this done purely by looking at some fixed address bits across the ranges?

Once we are at each directory controller, each such controller could in theory connect to more than a single channel of memory, and then we need to interleave once again, but now it gets complicated. The crossbar is now responsible for an interleaved range for every range in system.mem_ranges, and then we again stripe across a number of channels?

This means the memory controller (and ultimately AbstractMemory) sees a number of striped ranges, and the crossbar is not responsible for a contiguous range, but rather a stripe from a contiguous range.

Is that right?

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1. Nilay Vaish Oct. 21, 2014, 8:51 a.m. (Oct. 21, 2014, 8:51 a.m.)

   * Each directory controller is assigned some bit pattern that it is responsible for.
   
   * Currently ruby's directory controllers do not have any sense of multiple memory ranges.
     They assume that the underlying memory range is contiguous.
   
   * The crossbar I presume would see stripes from multiple address ranges.
   
   Overall, I think your understanding is correct (or same as mine).