Review Board 2.0.15


ARM: Don't return the result of a table walk the same cycle it's returned.

Review Request #257 - Created Oct. 2, 2010 and submitted

Information
Ali Saidi
gem5
Reviewers
Default 
ARM: Don't return the result of a table walk the same cycle it's returned.

The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.

Also prevent multiple outstanding table walks from occuring at once.

   

  


 


 

  

  









  
 


  

 
















 



 

  


 


  



   

   
Steve Reinhardt

   
Posted  (Oct. 15, 2010, 10:33 a.m.)


  


  


  

   
The first sentence of the commit message is pretty confusing (self-contradicting if you read it wrong).

I don't object to this particular change, but isn't it just working around a design flaw in TimingSimpleCPU, and wouldn't it be better to fix that instead?

Also, assuming the answer there is no, shouldn't the same fix be applied in the x86 table walker too?



  

   

   
    
    

   
  1. 
    
    
     
    
      
     
    
     
    I think it's pretty reasonable that the table walker will take a cycle after it gets the required data to provide it to the CPU. I don't know that we want to convolute the code in the timing "simple" cpu model anymore. 
    
    
    
   
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  2. 
    
    
     
    
      
     
    
     
    Yea, my hope was that we might find a way to fix this while simplifying TimingSimpleCPU... I agree, I have no desire to make it more complicated.
    
    
    
   
    3.