I'll definitely try to do that in my code, but the problem is in TimingSimpleCPU. I found this problem if I hook TimingSimpleCPU directly to the crossbar (i.e. without an L1 I/D cache). I know this isn't a very common configuration, but it seems like something the crossbar should support.

I'm not an expert in how the TimingSimpleCPU code works, and from a cursory look I don't understand exactly where the request/response logic is. This problem definitely occurs in the instruction fetch logic, and maybe in the data fetch logic as well.

Here's a link to the config file I'm using: http://pages.cs.wisc.edu/~david/courses/cs752/Spring2015/gem5-tutorial/_downloads/simple.py (it should be available outside of Wisconsin). This config file works before revision 10656, but rev 10656 breaks it.

I don't really have time right now to dig into the TimingSimpleCPU code, so I'm going to have the class use gem5-stable. Going forward, do we want to fix TimingSimpleCPU, or is there something else we should do?

I can have a look, it shouldn't be too complicated.

I'd say let's just fix the timing cpu.

Ok. I'll drop this review request, then.

Have a look at: http://reviews.gem5.org/r/2620/