mem: implement x86 locked accesses in timing-mode classic cache
Review Request #2691 - Created March 14, 2015 and updated - Latest diff uploaded
| Information | |
|---|---|
| Steve Reinhardt | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 11444:8a1419dbbfa6 --------------------------- mem: implement x86 locked accesses in timing-mode classic cache Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, use a combination of clearing permission bits and leaving an MSHR in place to prevent accesses & snoops from touching a locked block between the read and write parts of an locked RMW sequence.