slicc: support for multiple cache entry types in the same state machine

Information
Submitter:	Tony Gutierrez
Repository:	gem5
Branch:	default
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Description

Changeset 10824:91803d728dc0
---------------------------
slicc: support for multiple cache entry types in the same state machine

To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:

  structure(DirEntry, desc="...", interface="AbstractCacheEntry",
            main="false") {

...and the primary type would be declared:

  structure(Entry, desc="...", interface="AbstractCacheEntry") {

Testing Done

I will think more about this.  This is not at all what I would want to do.

Nilay Vaish May 14, 2015, 7:44 a.m. (May 14, 2015, 7:44 a.m.)

I thought about this patch.  It is not what I would have done had I wanted to
define multiple structures that inherit from AbstractCacheEntry.  In retrospect,
the set of decisions where in we decided to implicitly pass cache and tbe entries
around seem very bad.  But I hardly think AMD is willing to do the work required 
to fix SLICC.  I am OK with this patch getting committed.

Can you give a more detailed description of the use case? In what scenario do you want separate entry types?

Brad Beckmann May 13, 2015, 1:55 p.m. (May 13, 2015, 1:55 p.m.)

As Jason points out below, this type of situation can happen in many scenarios. Joel your idea would require that the directory and cache tags be manged by a single structure. That may not be what one always wants to do.

I think this seems reasonable. For instance, if you want to create a single state machine with both an L3 and a directory (e.g., the directory is the L3 cache tags), this would be useful. I could see many other use cases as well.

Assuming this gets through the review process, it would be good to add a note to the wiki about the changes in the SLICC syntax.

Joel Hestness May 13, 2015, 9:24 a.m. (May 13, 2015, 9:24 a.m.)

I don't understand your example. If the directory is the L3 cache tags, then you should only need 1 entry type with a variable indicating presence in the L3.

Brad Beckmann May 13, 2015, 1:55 p.m. (May 13, 2015, 1:55 p.m.)
```
I'm happy to add this description to the wiki if it helps.
```

Any more comments on this patch? It sounds like the discussion as been resolved, but we only have one ship it.

I can be ok with this for now.

For future reference, I think I like what Nilay is suggesting in the email thread: There should be a way for a SLICC state machine to designate which entry type (descended from AbstractCacheEntry) is used in transition and action headers, but the designation should be done outside of the type declaration itself. This designation might require adding a keyword or adjusting the machine declaration header, which would require adjustments to existing protocols. However, I think this solution makes more sense than the way this patch handles it, because it would allow arbitrary inheritance of AbstractCacheEntry without any special flags in the type declaration.

Description:

~		Changeset 10851:88582222762b
	~	Changeset 10824:91803d728dc0

		slicc: support for multiple cache entry types in the same state machine

		To have multiple Entry types (e.g., a cache Entry type and
		a directory Entry type), just declare one of them as a secondary
		type by using the pair 'main="false"', e.g.:

		structure(DirEntry, desc="...", interface="AbstractCacheEntry",
		main="false") {

		...and the primary type would be declared:

		structure(Entry, desc="...", interface="AbstractCacheEntry") {

Diff:

Revision 2 (+7 -4)

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src/mem/slicc/symbols/StateMachine.py

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Changeset 10851:88582222762b

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Status: Closed (submitted)