x86: decode instructions with vex prefix
Review Request #2827 - Created May 17, 2015 and submitted
| Information | |
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| Nilay Vaish | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10874:65214a5bb5a6 --------------------------- x86: decode instructions with vex prefix This patch updates the x86 decoder so that it can decode instructions with vex prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3. Note that none of the instructions have been implemented yet. The implementations would be provided in due course of time.
Review request changed
Updated (May 27, 2015, 3:29 p.m.)
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Revision 2 (+1648 -7) |
Review request changed
Updated (June 16, 2015, 4:15 p.m.)
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Revision 3 (+1704 -7) |
Posted (July 6, 2015, 2:58 p.m.)
I see incremental changes between revisions and plenty of vector instructions still unimplemented, is this considered complete or it is still in development?