ruby: Add ReadRespWithInvalidate support, fixes MESI consistency bug
Review Request #2842 - Created May 21, 2015 and updated
| Information | |
|---|---|
| Marco Elver | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10839:2978f9ed5e7a
ruby: Add ReadRespWithInvalidate support, fixes MESI consistency bug
A sunk Inv in the IS state needs to be propagated to the LQ eventually. Thus far, Ruby has no support for properly propagating an invalidate along with a ReadResp.
This patch adds support for ReadRespWithInvalidate upon a readCallback, so that the LQ can properly deal with such a request.
Note that we cannot just do a forward_eviction in the IS,Inv transition, as other outstanding loads in the LQ after the one for which we get the Inv, may be satisfied (with old values) inbetween the Inv and IS_I,Data transitions.
The scenarios are the same as for the problem fixed in revision 10575 (which addressed the LSQ side of things).
Tester no longer finds bug. Note this was done with an (older) version of gem5 that was still happy with Ruby+O3CPU. A quick run with ruby-tester yielded no obvious issues.
NOTE: I'm not entirely happy with the "Hack?" code. If someone can possibly suggest how we can add a nicer way to add support for ReadRespWithInvalidate to Ruby, then that'd probably be better than what this patch does.
Issue Summary
| Description | From | Last Updated | Status |
|---|---|---|---|
| Yes, hack! :-) Surely this should be done as part of the hitCallback rather? | Andreas Hansson | May 31, 2015, 3:33 a.m. | Open |
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src/mem/ruby/system/Sequencer.cc (Diff revision 1) -
Yes, hack! :-)
Surely this should be done as part of the hitCallback rather?
Question below:
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src/mem/protocol/MESI_Two_Level-L1cache.sm (Diff revision 1) -
Why introduce a new action here? It seems like the simplier way to handle this situation is insert the forward_eviction_to_cpu action after the hx_load_hit callback rather than introduce a new action and additional complexity in the sequencer.
