x86, o3: Enabling x86 TLBs for multiple hardware threads

Information
Submitter:	Alexandru Dutu
Repository:	gem5
Branch:	default
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Description

Changeset 10860:f4565ce598dd
---------------------------
x86, o3: Enabling x86 TLBs for multiple hardware threads
This patch extends the x86 TLB to be shared among multiple hardware threads.
Its size will represent the total number of TLB entries that can be allocated
to all threads.

Testing Done

Quick regressions passed for all ISAs.

I'm confused about the commit message: Based on the handling of the freeList and evictions, it seems like the only limit on TLB entries per thread is the total TLB size, so there isn't a statically set number of entries per thread. Am I missing something? If not, can you please fix the commit message?

Alexandru Dutu May 29, 2015, 2:06 p.m. (May 29, 2015, 2:06 p.m.)

Actually the commit message has not got updated to reflect the changes in the code. Thanks for pointing this!

Change Summary:

Updating commit message.

Description:

~		Changeset 10860:f4565ce598dd
~
~		x86, o3: Enabling x86 TLBs for multiple hardware threads
	~	Changeset 10860:f4565ce598dd
	~	---------------------------
	~	x86, o3: Enabling x86 TLBs for multiple hardware threads
		This patch extends the x86 TLB to be shared among multiple hardware threads.
~		Its size will represent the number of all TLB entries that can be allocated to
~		all threads, therefore there is statically assigned number of entries per
	~	Its size will represent the total number of TLB entries that can be allocated
	~	to all threads.
-		thread.

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Change Summary:

Description:

Changeset 10860:f4565ce598dd