x86, o3: Enabling x86 TLBs for multiple hardware threads
Review Request #2853 - Created May 28, 2015 and discarded
| Information | |
|---|---|
| Alexandru Dutu | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10860:f4565ce598dd --------------------------- x86, o3: Enabling x86 TLBs for multiple hardware threads This patch extends the x86 TLB to be shared among multiple hardware threads. Its size will represent the number of all TLB entries that can be allocated to all threads, therefore there is statically assigned number of entries per thread.
Quick regressions passed for all ISAs.