Review Board 2.0.15


ARM: Add support for switching CPUs

Review Request #290 - Created Nov. 8, 2010 and submitted

Information
Ali Saidi
gem5
Reviewers
Default 
ARM: Add support for switching CPUs

   

  


 


 

  

  









  
 


  

 
















 



 

  


 


  



   

   
Gabe Black

   
Posted  (Nov. 9, 2010, 3:37 a.m.)


  


  


  

   



  

   

   
    
    
   


  




   







    

     
     

      

       
        

         
          src/cpu/simple_thread.cc
          

           (Diff revision 1)

          
         
        

       
       
        
 


        
 


       
      

     

    

    


     
What happens to the old TLB? What if you wanted to switch to a new one? I'm assuming this is so state cached in the TLB gets transfered, but I don't think this is the right way to do it. Maybe in the copyRegs function you can transfer state between TLBs? Maybe it already is because you're updating miscregs, and that should update the TLB. Maybe you need to set more miscregs with effects.




  

   

   
    
    

   
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    In this case you keep the old TLB. I this this is really desired behavior, because you want that structure to be warmed up on the switch and if you switch to a new one it's empty. It's also so whatever the TLB is connected to it stays connected. In the case of ISAs that require table walkers the code would need to figure that out and move their ports too. 
    
    
    
   
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    I mean the original TLB of the new context. You'll just overwrite the pointer without cleaning up references to original object, it's memory, etc. You'll preserve old connections, but any new connections will be left hanging. 
    
    
    
   
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