I found one instance where I think the line got too long, but there was ALOT of stuff here, and I stopped really looking carefully after a while. I have a comment as far as the quantity of new classes (below). Also, I think you may have overly applied the SIMDness. VFP3 instructions are "vector" instructions in the sense that they apply the same operation multiple times, but I got the impression that they literally were applied multiple times serially instead of in parallel by repeating them with different register indexes. I think I implemented them that way using microcode, but it's been a while.

src/arch/arm/isa/insts/fp.isa (Diff revision 1)

My counting may be off, but I think these are now more than 80 characters long. If they are, please wrap them.

src/cpu/FuncUnit.py (Diff revision 1)

What exactly is an add and accumulate? Isn't that a little redundant? Since shift isn't broken out in the non-simd classes, it can probably fold into Alu, as can ShiftAcc. Do you think MultAcc is a genuinely different operation from Mult? Generally I like the idea of new Simd op classes, but I think you might have been overly specific.