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config: Fail if not using all L2 caches in ruby protocols

Review Request #2970 - Created July 14, 2015 and updated

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David Hashe
gem5
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Reviewers
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Changeset 10923:17785cb5a672
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config: Fail if not using all L2 caches in ruby protocols

In the MESI_Three_Level, MESI_Two_Level, MOESI_CMP_directory, and MOESI_CMP_token protocols, if the num_l2caches option is not a power of 2, then all cache banks above the next lowest power of 2 are not addressed and are never used (cache bank selection takes place in mapAddressToRange within src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping).

This changeset adds asserts to the configuration files of the affected protocols to make sure that num_l2caches is a power of 2.

A related behavior is documented in http://gem5.org/Coherence-Protocol-Independent_Memory_Components#Parameters_3, at the bottom of the section on start_index_bit.


   

Issue Summary

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Description From Last Updated Status
To check for power of two, do (v & (v-1)) == 0. Nilay Vaish July 14, 2015, 9:32 a.m. Open
Posted (July 14, 2015, 8:01 a.m.)

Are you assuming that physical memory size is a power of 2?

  1. If the physical memory size is not a power of 2, the issue still arises. The problem lies with how the addresses are assigned to L2 caches.

Posted (July 14, 2015, 9:32 a.m.)



  
configs/ruby/MESI_Three_Level.py (Diff revision 1)
 
 

To check for power of two, do (v & (v-1)) == 0.

  1. That's more efficient, but I'm not sure it's more readable, and I don't think efficiency really matters in this case.

    In C++, we have an isPowerOf2() function in src/base/intmath.hh; perhaps we need something similar in python?