Invalidating TLB entry on page fault in x86

Information
Submitter:	Swapnil Haria
Repository:	gem5
Branch:	default
Bugs:
Depends On:
Reviewers
Groups:	Default
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Description

Changeset 11179:f8f3c06af8b1
---------------------------
Invalidating TLB entry on page fault in x86

As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel.  This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a bash
file). Ensured that page fault rate drops drastically and observed reduction in
boot time from order of hours to minutes for linux kernel v3.8 and v3.11

Testing Done

Description:

~		Changeset 11179:7f23629b88d3
	~	Changeset 11179:f5cb3abbb62b

		Invalidating TLB entry on page fault in x86

		As per the x86 architecture specification, matching TLB entries need to be
		invalidated on a page fault. For instance, after a page fault due to inadequate
		protection bits on a TLB hit, the TLB entry needs to be invalidated. This
		behavior is clearly specified in the x86 architecture manuals from both AMD and
		Intel. This invalidation is missing currently in gem5, due to which linux
		kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
		a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
		removes a tlb flush on updating page table entries in x86.

		Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
		due to repeated page faults (~300000 before the first print statement in a bash
		file). Ensured that page fault rate drops drastically and observed reduction in
		boot time from order of hours to minutes for linux kernel v3.8 and v3.11

Diff:

Revision 2 (+12)

Show changes

	src/arch/x86/tlb.hh
	src/arch/x86/tlb.cc

Ship It!

Page faults don't actually happen when they're detected by the TLB, they happen when the page fault is invoked later. That may never happen if an instruction is running speculatively, or potentially if a translation is done for some reason other than instruction execution. Side effects like the one you're adding should happen during the invoke, not when the fault is detected.

Summary:

-	Invalidating TLB entry on page fault in x86
+	imported patch faults.cc

Description:

~		Changeset 11179:f5cb3abbb62b
	~	Changeset 11179:98e703a98b4a

~		Invalidating TLB entry on page fault in x86
	~	imported patch faults.cc
-
-		As per the x86 architecture specification, matching TLB entries need to be
-		invalidated on a page fault. For instance, after a page fault due to inadequate
-		protection bits on a TLB hit, the TLB entry needs to be invalidated. This
-		behavior is clearly specified in the x86 architecture manuals from both AMD and
-		Intel. This invalidation is missing currently in gem5, due to which linux
-		kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
-		a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
-		removes a tlb flush on updating page table entries in x86.
-
-		Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
-		due to repeated page faults (~300000 before the first print statement in a bash
-		file). Ensured that page fault rate drops drastically and observed reduction in
-		boot time from order of hours to minutes for linux kernel v3.8 and v3.11

Diff:

Revision 3 (+4 -1)

Show changes

	src/arch/x86/faults.hh
	src/arch/x86/faults.cc

Summary:

-	imported patch faults.cc
+	Invalidating TLB entry on page fault in x86

Description:

~		Changeset 11179:98e703a98b4a
	~	Changeset 11179:f8f3c06af8b1

~		imported patch faults.cc
	~	Invalidating TLB entry on page fault in x86
	+
	+	As per the x86 architecture specification, matching TLB entries need to be
	+	invalidated on a page fault. For instance, after a page fault due to inadequate
	+	protection bits on a TLB hit, the TLB entry needs to be invalidated. This
	+	behavior is clearly specified in the x86 architecture manuals from both AMD and
	+	Intel. This invalidation is missing currently in gem5, due to which linux
	+	kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
	+	a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
	+	removes a tlb flush on updating page table entries in x86.
	+
	+	Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
	+	due to repeated page faults (~300000 before the first print statement in a bash
	+	file). Ensured that page fault rate drops drastically and observed reduction in
	+	boot time from order of hours to minutes for linux kernel v3.8 and v3.11

Diff:

Revision 4 (+4 -1)

Show changes

	src/arch/x86/faults.hh
	src/arch/x86/faults.cc

Thanks for changing this around.

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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Description:

Changeset 11179:7f23629b88d3

Changeset 11179:f5cb3abbb62b

Diff:

Summary:

Description:

Changeset 11179:f5cb3abbb62b

Changeset 11179:98e703a98b4a

Diff:

Summary:

Description:

Changeset 11179:98e703a98b4a

Changeset 11179:f8f3c06af8b1

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Status: Closed (submitted)