Changeset 11187:e5e740fac1fb
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cpu: Add store-access operations

This patch was created by Bihn Pham during his internship at AMD.

This patch adds decoupled store operations that are commonly used by
high-performance processors. The patch modifies the O3 CPU model to issue
StoreAccess operations as soon as possible to acquire exclusive permission for
eventual stores. Later data store operations behave as normal.

In the classic memory model, StoreAccess requests are treated as HardPFExReq
and share the existing prefetch queue. Therefore, they affect performance only
if the prefetcher is enabled in the classic model.

In Ruby, StoreAccess requests are treated as RubyStore with NULL data field.