arm: remote GDB: rationalize structure of register offsets
Review Request #3207 - Created Nov. 13, 2015 and submitted
| Information | |
|---|---|
| Boris Shingarov | |
| gem5 | |
| Reviewers | |
| Default | |
arm: remote GDB: rationalize structure of register offsets Currently, the wire format of register values in g- and G-packets is modelled using a union of uint8/16/32/64 arrays. The offset positions of each register are expressed as a "register count" scaled according to the width of the register in question. This results in counter- intuitive and error-prone "register count arithmetic", and some formats would even be altogether unrepresentable in such model, e.g. a 64-bit register following a 32-bit one would have a fractional index in the regs64 array. Another difficulty is that the array is allocated before the actual architecture of the workload is known (and therefore before the correct size for the array can be calculated). With this patch I propose a simpler mechanism for expressing the register set structure. In the new code, GdbRegCache is an abstract class; its subclasses contain straightforward structs reflecting the register representation. The determination whether to use e.g. the AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made by polymorphically dispatching getregs() to the concrete subclass. The subclass is not instantiated until it is needed for actual g-/G-packet processing, when the mode is already known. This patch is not meant to be merged in on its own, because it changes the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*, so as it stands right now, it would break the other architectures. In this patch only the base and the ARM code are provided for review; once we agree on the structure, I will provide src/arch/*/remote_gdb.* for the other architectures; those patches could then be merged in together.
Tested in SE mode with both AArch32 and AArch64, using gdb 7.10 configured with --target=arm-linux-gnueabihf and --target=aarch64-linux-gnu, as well as with our internal gdb RSP client.
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src/base/remote_gdb.hh (Diff revision 1) -
would like to see doxygen documentation for these methods
Overall this seems like a sensible approach to me
Looks like a good design to me. I'm currently testing it in aarch32 and it seems to work. There are a couple of nits below, but the code looks good overall.
There is one ARM-specific high-level issues that you will need to consider before committing this. What happens if the CPU switches between aarch32 and aarch64? As far as I can tell, the gdbregs() won't switch modes if this happens.
Feel free to add yourself (or whoever owns the copyright of your work) to the copyright header in the files where you have made significant changes.
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src/arch/arm/remote_gdb.cc (Diff revision 2) -
This could go into the base class now.
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src/arch/arm/remote_gdb.cc (Diff revision 2) -
Nit: New line after between parameter list and {.
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src/base/remote_gdb.hh (Diff revision 2) -
getRegs()
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src/base/remote_gdb.hh (Diff revision 2) -
setRegs()
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src/base/remote_gdb.hh (Diff revision 2) -
Consider making this a unique_ptr.
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src/base/remote_gdb.hh (Diff revision 2) -
This should probably be gdbRegs() and you probably don't want to make it purely virtual unless you plan to fix up all other architectures in the same changeset.
Nit: The * should be next to the function name and not the type to be consistent with the rest of the file.
Thanks for updating the review. I think the overall design is good, but the latest revision introduced a bug in the way the register cache is handled. Again, I'm happy with the overall design, so just nail the last couple of things and this is good to go.
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src/arch/arm/remote_gdb.cc (Diff revision 3) -
Won't this leak memory with the current use cases? (Actually, it seems like it won't work at all since a lot of the calls will now work on different objects)
What I meant in the previous review round by using a unique_ptr here was that you'd store the cache in a unique_ptr in the RemoteGDB object. If the unique_ptr isn't set or the CPU mode has changed, you instantiate a (new) reg cache, then return a naked pointer from the unique_ptr. I'm sorry if I was unclear.
Another option would be to store one aarch64 and one aarch32 reg cache in the ARM implementation of the RemoteGDB class and just return the right pointer/reference here. I imagine you'd do that for ISAs that need just one reg cache implementation.
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src/base/remote_gdb.hh (Diff revision 3) -
It might make sense to make this a uint8_t instead. We probably want to manipulate it as a char array most of the time. Also, it might make sense to make a const version of this as well.
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src/base/remote_gdb.hh (Diff revision 3) -
I'd prefer if this was called size() instead. That's what I'd expect from most container types.
Also, please make it const wrt the object.
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src/base/remote_gdb.hh (Diff revision 3) -
Make this const wrt the object.
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src/arch/arm/remote_gdb.cc (Diff revision 4) -
I'd just loop over these, but don't worry about it.
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src/arch/arm/remote_gdb.cc (Diff revision 4) -
Dito.
Thanks for sorting this out! Remind me to buy you a beer if we ever meet in person! :)
Minor nits above. Don't worry about it unless you need to update for some other reason. Also, try and get an ACK from someone who cares about x86 (e.g., Steve).
I have been testing this a bit with the hello world program in SE mode for x86. It seems fine to me. Thanks for cleaning this up!
