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src/cpu/o3/iew_impl.hh (Diff revision 1)

Why not just not return a fault in these cases?

src/cpu/o3/iew_impl.hh (Diff revision 1)

So the code outside the if block executes normally and the prefetch, if it faults, just silently goes away. 

1. Gabe Black Dec. 9, 2010, 11:03 a.m. (Dec. 9, 2010, 11:03 a.m.)

   Oooooh, I got it now. I initially thought this was the instruction's execute method returning the fault, but now I see that's not the case (right?). This makes sense now.

src/arch/arm/tlb.cc (Diff revision 1)

It seems to me like we ought to have a generic check in the CPU models that prevents prefetches to uncacheable locations rather than burying this in the TLB and requiring every ISA to make this check.  (Which leads to the question of how/whether this is handled in other ISAs...)

1. Ali Saidi Jan. 5, 2011, 12:51 a.m. (Jan. 5, 2011, 12:51 a.m.)

   Prefetches aren't implemented in Alpha so this hasn't been an issue. I don't know that I agree it should be in a generic place because I don't know that uncachable is equivalent to non-prefetchable. For example, an memory could be marked cacheable but not prefetchable in sparc if memory serves (same is probably true for some ASI accesses). I think the TLB really needs to make the decision because it's got all of the relevant information.