Changeset 11459:faf70a6f13ed
o3: Clarify meaning of cachePorts variable in lsq_unit.hh 
cachePorts currently constrains the number of store packets written to the

D-Cache each cycle), but loads currently affect this variable. This leads 

to unexpected congestion (e.g., setting cachePorts to a realistic 1 will 

in fact allow a store to WB only if no loads have accessed the D-Cache 

this cycle). In the absence of arbitration, this patch decouples how many 

loads can be done per cycle from how many stores can be done per cycle.

util/regress -v --builds=ARM passes with 0% differences (expected: cachePorts defaults to 200, so functionally, the patch changes nothing for the default parameters).