Create four new L2 types of cache architectures for the classic memory system.

The classic memory system has one option for L2 cache architecture: a single shared L2 cache.

This patch allows the designer to employ four new types:

A shared instruction and data L2 cache.
Private L2 caches (one per core).
Private instruction and data L2 caches (two per core).
Paired L2 cache (user-defined number of L2 caches per cluster of core).

Additional command-options were created to control the latency and MSHR queue size of such caches.

In addition, this patch does not influence existing simulations -- see the testing section for more details.

All systems were tested using the ARM ISA and the canneal benchmark (from PARSEC) using the simmedium input set.

All new command-options were tested.
The result prefixed with the string "vanilla" is a simulation without the patch. This shows that the patch does not change the statistics of the system for the --l2cache scenario (only the number of executed instructions on the host are changed due to the patches).
results: http://tinyurl.com/l2-caches-gem5