arm, config: added support for ex5 model of big.LITTLE

Information
Submitter:	Anastasiia Butko
Repository:	gem5
Branch:	default
Bugs:
Depends On:
Reviewers
Groups:	Default
People:

Description

Changeset 11687:b3946ea8b081
---------------------------
arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE
cores, ex5_big and ex5_LITTLE instead of the default
'arm_detailed' and 'minor' cpus. The ex5 model is based
on the Samsung Exynos 5 Octa (5422) SoC. Operation and
memory hierarchy latencies have been calibrated using the
lmbench micro-benchmark suite. The preliminary validation
results have been published as:
'Full-System Simulation of big.LITTLE Multicore Architecture
for Performance and Energy Exploration', in International
Symposium on Embedded Multicore/Many-core Systems-on-Chip
(MCSoC'16), Lyon, France (Sep, 2016).

Reported-by: Anastasiia Butko <abutko@lbl.gov>

Testing Done

Issue Summary

Description	From	Last Updated	Status
Rather than having an extra parameter, could you make a subclass of the BigCluster? If this would introduce a lot ...	Jason Lowe-Power	Oct. 19, 2016, 9:47 p.m.	Resolved
Why use CpuConfig here? Why not just use ex5_LITTLE.ex5_LITTLE? I guess this applies to the "arm_detailed" too.	Jason Lowe-Power	Oct. 20, 2016, 9:38 a.m.	Resolved

Status: Discarded

Status: Re-opened

The diff doesn't apply correctly. Could you fix and re-upload?

Anastasiia Butko Oct. 17, 2016, 9:27 p.m. (Oct. 17, 2016, 9:27 p.m.)

I've combined both patches in one. And these changes do not include the MemConfig support.

Summary:

-	arm, config: [1/2] added support for ex5 model of big.LITTLE
+	arm, config: added support for ex5 model of big.LITTLE

Description:

~		Changeset 11671:11597c9e6f31
	~	Changeset 11670:cccf07bc045e
		---------------------------
~		arm, config: [1/2] added support for ex5 model of big.LITTLE
	~	arm, config: added support for ex5 model of big.LITTLE

~		This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default
~		'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and
~		memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation
~		results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture
~		for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip
	~	This patch enables using calibrated big and LITTLE
	~	cores, ex5_big and ex5_LITTLE instead of the default
	~	'arm_detailed' and 'minor' cpus. The ex5 model is based
	~	on the Samsung Exynos 5 Octa (5422) SoC. Operation and
	~	memory hierarchy latencies have been calibrated using the
	+	lmbench micro-benchmark suite. The preliminary validation
	+	results have been published as:
	+	'Full-System Simulation of big.LITTLE Multicore Architecture
	+	for Performance and Energy Exploration', in International
	+	Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

~		Reported-by: Anastasiia Butko abutko@lbl.gov
	~	lat_ops bench results:
	+	----------------------------------------------
	+	big LITTLE
	+	ops SoC gem5 SoC gem5
	+	----------------------------------------------
	+	integer bit: 0.5 0.48 0.72 0.7
	+	integer add: 0.5 0.55 0.72 0.4
	+	integer mul: 1.56 1.68 2.16 1.87
	+	integer div: 45.36 36.32 53.3 47.32
	+	integer mod: 6.56 18.55 17.37 18.02
	+	int64 bit: 0.51 0.98 1.45 1.42
	+	uint64 add: 0.63 0.98 1.56 0.93
	+	int64 mul: 2.52 2.13 3.64 4.68
	+	int64 div: 92.61 195.52 213.14 197.63
	+	int64 mod: 47.91 146.78 135.41 138.91
	+	float add: 2.52 2.71 2.88 2.61
	+	float mul: 3.02 2.84 2.88 2.73
	+	float div: 9.07 8.94 12.98 2.82
	+	double add: 2.52 2.71 2.88 2.61
	+	double mul: 3.02 2.84 5.04 2.73
	+	double div: 16.13 10.43 23.03 2.81
	+
	+	lat_mem_rd bench results:
	+	----------------------------------------------
	+	big LITTLE
	+	cache mem SoC gem5 SoC gem5
	+	----------------------------------------------
	+	l1/l1 0.5K 4 4 3 3
	+	1K 4 4 3 3
	+	2K 4 4 3 3
	+	3K 4 4 3 3
	+	4K 4 4 3 3
	+	6K 4 4 3 3
	+	8K 4 4 3 3
	+	12K 4 4 3 3
	+	16K 4 18 3 3
	+	24K 13 17 3 3
	+	32K 18 18 6 11
	+	l2/l2 48K 23 20 9 14
	+	64K 22 23 11 14
	+	96K 23 23 13 14
	+	128K 23 23 14 15
	+	192K 23 23 15 17
	+	256K 23 23 17 17
	+	384K 23 24 29 17
	+	512K 23 24 59 39
	+	l2/Mem 768K 23 24 86 97
	+	1M 23 24 112 110
	+	1.5M 35 25 153 147
	+	2M 81 56 165 172
	+	Mem/Mem 3M 167 162 170 179
	+	4M 217 213 171 182
	+	6M 251 247 171 182
	+	8M 260 257 171 182
	+	12M 263 261 171 182
	+	16M 265 261 171 182
	+
	+	Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 2 (+371 -9)

Show changes

	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

Description:

~		Changeset 11670:cccf07bc045e
	~	Changeset 11670:c9fd4bc4a0cf
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

		lat_ops bench results:
		----------------------------------------------
		big LITTLE
		ops SoC gem5 SoC gem5
		----------------------------------------------
		integer bit: 0.5 0.48 0.72 0.7
		integer add: 0.5 0.55 0.72 0.4
		integer mul: 1.56 1.68 2.16 1.87
		integer div: 45.36 36.32 53.3 47.32
		integer mod: 6.56 18.55 17.37 18.02
		int64 bit: 0.51 0.98 1.45 1.42
		uint64 add: 0.63 0.98 1.56 0.93
		int64 mul: 2.52 2.13 3.64 4.68
		int64 div: 92.61 195.52 213.14 197.63
		int64 mod: 47.91 146.78 135.41 138.91
		float add: 2.52 2.71 2.88 2.61
		float mul: 3.02 2.84 2.88 2.73
		float div: 9.07 8.94 12.98 2.82
		double add: 2.52 2.71 2.88 2.61
		double mul: 3.02 2.84 5.04 2.73
		double div: 16.13 10.43 23.03 2.81

		lat_mem_rd bench results:
		----------------------------------------------
		big LITTLE
		cache mem SoC gem5 SoC gem5
		----------------------------------------------
		l1/l1 0.5K 4 4 3 3
		1K 4 4 3 3
		2K 4 4 3 3
		3K 4 4 3 3
		4K 4 4 3 3
		6K 4 4 3 3
		8K 4 4 3 3
		12K 4 4 3 3
		16K 4 18 3 3
		24K 13 17 3 3
		32K 18 18 6 11
		l2/l2 48K 23 20 9 14
		64K 22 23 11 14
		96K 23 23 13 14
		128K 23 23 14 15
		192K 23 23 15 17
		256K 23 23 17 17
		384K 23 24 29 17
		512K 23 24 59 39
		l2/Mem 768K 23 24 86 97
		1M 23 24 112 110
		1.5M 35 25 153 147
		2M 81 56 165 172
		Mem/Mem 3M 167 162 170 179
		4M 217 213 171 182
		6M 251 247 171 182
		8M 260 257 171 182
		12M 263 261 171 182
		16M 265 261 171 182

		Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 3 (+385 -9)

Show changes

	configs/common/CpuConfig.py
	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

There are quite a few whitespace errors. Either look at the diff on reviewboard to see where the big read boxes are, or run the style checker, which should fix them.

Would it make more sense to put the core model configurations in their own directory. Maybe configs/cpu_models? Or configs/example/arm/cpu_models? Maybe this is a more long-term question and it doesn't matter for this. What do other think?

Anastasiia Butko Oct. 18, 2016, 9:05 p.m. (Oct. 18, 2016, 9:05 p.m.)

I believe this option is related to the 'make config/common a Python package' commit and the upcoming re-organization of the config structure.

Anastasiia Butko Oct. 18, 2016, 9:33 p.m. (Oct. 18, 2016, 9:33 p.m.)

BTW, could someone commit the patch #3665 so I may update this one on the top of MemConfig changes?

configs/example/arm/fs_bigLITTLE.py (Diff revision 3)

Rather than having an extra parameter, could you make a subclass of the BigCluster? If this would introduce a lot more code, you shouldn't do it, but I think it would make things cleaner.

Show all issues

Anastasiia Butko Oct. 18, 2016, 9:12 p.m. (Oct. 18, 2016, 9:12 p.m.)

Indeed, this will introduce more code. What about adding two new options, --big-cpus-type and --little-cpus-type, while removing --ex5 and --atomic?

Jason Lowe-Power Oct. 19, 2016, 8:47 a.m. (Oct. 19, 2016, 8:47 a.m.)

I'm a little surprised that it would introduce much more code. Overall, I think it's much better to use object-oriented designs like inheritance instead of passing extra parameters to the constructor.

You definitely shouldn't add more command line parameters! Just --ex5 is fine. I like this script because it's short and sweet without loads of command line options. IMO, if you want to model a system that has one ex5 core and one default core, you can modify the script or create a new script to do that.

Anastasiia Butko Oct. 19, 2016, 9:53 p.m. (Oct. 19, 2016, 9:53 p.m.)

OK, I use one single option. But intead of creating multiple big_Cluater/little_Cluster classes I forward the desired type of core. It can be easily modified by user in case he wants a different configuration.

configs/example/arm/fs_bigLITTLE.py (Diff revision 3)

Why use CpuConfig here? Why not just use ex5_LITTLE.ex5_LITTLE?

I guess this applies to the "arm_detailed" too.

Show all issues

Anastasiia Butko Oct. 18, 2016, 9:20 p.m. (Oct. 18, 2016, 9:20 p.m.)

Sure. But again, if X-cpu-type option is used it allows configuring elastic traces, etc. in future

Description:

~		Changeset 11670:c9fd4bc4a0cf
	~	Changeset 11687:0206e45662b9
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

		lat_ops bench results:
		----------------------------------------------
		big LITTLE
		ops SoC gem5 SoC gem5
		----------------------------------------------
		integer bit: 0.5 0.48 0.72 0.7
		integer add: 0.5 0.55 0.72 0.4
		integer mul: 1.56 1.68 2.16 1.87
		integer div: 45.36 36.32 53.3 47.32
		integer mod: 6.56 18.55 17.37 18.02
		int64 bit: 0.51 0.98 1.45 1.42
		uint64 add: 0.63 0.98 1.56 0.93
		int64 mul: 2.52 2.13 3.64 4.68
		int64 div: 92.61 195.52 213.14 197.63
		int64 mod: 47.91 146.78 135.41 138.91
		float add: 2.52 2.71 2.88 2.61
		float mul: 3.02 2.84 2.88 2.73
		float div: 9.07 8.94 12.98 2.82
		double add: 2.52 2.71 2.88 2.61
		double mul: 3.02 2.84 5.04 2.73
		double div: 16.13 10.43 23.03 2.81

		lat_mem_rd bench results:
		----------------------------------------------
		big LITTLE
		cache mem SoC gem5 SoC gem5
		----------------------------------------------
		l1/l1 0.5K 4 4 3 3
		1K 4 4 3 3
		2K 4 4 3 3
		3K 4 4 3 3
		4K 4 4 3 3
		6K 4 4 3 3
		8K 4 4 3 3
		12K 4 4 3 3
		16K 4 18 3 3
		24K 13 17 3 3
		32K 18 18 6 11
		l2/l2 48K 23 20 9 14
		64K 22 23 11 14
		96K 23 23 13 14
		128K 23 23 14 15
		192K 23 23 15 17
		256K 23 23 17 17
		384K 23 24 29 17
		512K 23 24 59 39
		l2/Mem 768K 23 24 86 97
		1M 23 24 112 110
		1.5M 35 25 153 147
		2M 81 56 165 172
		Mem/Mem 3M 167 162 170 179
		4M 217 213 171 182
		6M 251 247 171 182
		8M 260 257 171 182
		12M 263 261 171 182
		16M 265 261 171 182

		Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 4 (+385 -9)

Show changes

	configs/common/CpuConfig.py
	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

Description:

~		Changeset 11687:0206e45662b9
	~	Changeset 11687:d06445524410
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

		lat_ops bench results:
		----------------------------------------------
		big LITTLE
		ops SoC gem5 SoC gem5
		----------------------------------------------
		integer bit: 0.5 0.48 0.72 0.7
		integer add: 0.5 0.55 0.72 0.4
		integer mul: 1.56 1.68 2.16 1.87
		integer div: 45.36 36.32 53.3 47.32
		integer mod: 6.56 18.55 17.37 18.02
		int64 bit: 0.51 0.98 1.45 1.42
		uint64 add: 0.63 0.98 1.56 0.93
		int64 mul: 2.52 2.13 3.64 4.68
		int64 div: 92.61 195.52 213.14 197.63
		int64 mod: 47.91 146.78 135.41 138.91
		float add: 2.52 2.71 2.88 2.61
		float mul: 3.02 2.84 2.88 2.73
		float div: 9.07 8.94 12.98 2.82
		double add: 2.52 2.71 2.88 2.61
		double mul: 3.02 2.84 5.04 2.73
		double div: 16.13 10.43 23.03 2.81

		lat_mem_rd bench results:
		----------------------------------------------
		big LITTLE
		cache mem SoC gem5 SoC gem5
		----------------------------------------------
		l1/l1 0.5K 4 4 3 3
		1K 4 4 3 3
		2K 4 4 3 3
		3K 4 4 3 3
		4K 4 4 3 3
		6K 4 4 3 3
		8K 4 4 3 3
		12K 4 4 3 3
		16K 4 18 3 3
		24K 13 17 3 3
		32K 18 18 6 11
		l2/l2 48K 23 20 9 14
		64K 22 23 11 14
		96K 23 23 13 14
		128K 23 23 14 15
		192K 23 23 15 17
		256K 23 23 17 17
		384K 23 24 29 17
		512K 23 24 59 39
		l2/Mem 768K 23 24 86 97
		1M 23 24 112 110
		1.5M 35 25 153 147
		2M 81 56 165 172
		Mem/Mem 3M 167 162 170 179
		4M 217 213 171 182
		6M 251 247 171 182
		8M 260 257 171 182
		12M 263 261 171 182
		16M 265 261 171 182

		Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 5 (+384 -10)

Show changes

	configs/common/CpuConfig.py
	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

Description:

~		Changeset 11687:d06445524410
	~	Changeset 11687:6293d0adc85c
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

		lat_ops bench results:
		----------------------------------------------
		big LITTLE
		ops SoC gem5 SoC gem5
		----------------------------------------------
		integer bit: 0.5 0.48 0.72 0.7
		integer add: 0.5 0.55 0.72 0.4
		integer mul: 1.56 1.68 2.16 1.87
		integer div: 45.36 36.32 53.3 47.32
		integer mod: 6.56 18.55 17.37 18.02
		int64 bit: 0.51 0.98 1.45 1.42
		uint64 add: 0.63 0.98 1.56 0.93
		int64 mul: 2.52 2.13 3.64 4.68
		int64 div: 92.61 195.52 213.14 197.63
		int64 mod: 47.91 146.78 135.41 138.91
		float add: 2.52 2.71 2.88 2.61
		float mul: 3.02 2.84 2.88 2.73
		float div: 9.07 8.94 12.98 2.82
		double add: 2.52 2.71 2.88 2.61
		double mul: 3.02 2.84 5.04 2.73
		double div: 16.13 10.43 23.03 2.81

		lat_mem_rd bench results:
		----------------------------------------------
		big LITTLE
		cache mem SoC gem5 SoC gem5
		----------------------------------------------
		l1/l1 0.5K 4 4 3 3
		1K 4 4 3 3
		2K 4 4 3 3
		3K 4 4 3 3
		4K 4 4 3 3
		6K 4 4 3 3
		8K 4 4 3 3
		12K 4 4 3 3
		16K 4 18 3 3
		24K 13 17 3 3
		32K 18 18 6 11
		l2/l2 48K 23 20 9 14
		64K 22 23 11 14
		96K 23 23 13 14
		128K 23 23 14 15
		192K 23 23 15 17
		256K 23 23 17 17
		384K 23 24 29 17
		512K 23 24 59 39
		l2/Mem 768K 23 24 86 97
		1M 23 24 112 110
		1.5M 35 25 153 147
		2M 81 56 165 172
		Mem/Mem 3M 167 162 170 179
		4M 217 213 171 182
		6M 251 247 171 182
		8M 260 257 171 182
		12M 263 261 171 182
		16M 265 261 171 182

		Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 6 (+384 -10)

Show changes

	configs/common/CpuConfig.py
	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

Description:

~		Changeset 11687:6293d0adc85c
	~	Changeset 11687:b3946ea8b081
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

		lat_ops bench results:
		----------------------------------------------
		big LITTLE
		ops SoC gem5 SoC gem5
		----------------------------------------------
		integer bit: 0.5 0.48 0.72 0.7
		integer add: 0.5 0.55 0.72 0.4
		integer mul: 1.56 1.68 2.16 1.87
		integer div: 45.36 36.32 53.3 47.32
		integer mod: 6.56 18.55 17.37 18.02
		int64 bit: 0.51 0.98 1.45 1.42
		uint64 add: 0.63 0.98 1.56 0.93
		int64 mul: 2.52 2.13 3.64 4.68
		int64 div: 92.61 195.52 213.14 197.63
		int64 mod: 47.91 146.78 135.41 138.91
		float add: 2.52 2.71 2.88 2.61
		float mul: 3.02 2.84 2.88 2.73
		float div: 9.07 8.94 12.98 2.82
		double add: 2.52 2.71 2.88 2.61
		double mul: 3.02 2.84 5.04 2.73
		double div: 16.13 10.43 23.03 2.81

		lat_mem_rd bench results:
		----------------------------------------------
		big LITTLE
		cache mem SoC gem5 SoC gem5
		----------------------------------------------
		l1/l1 0.5K 4 4 3 3
		1K 4 4 3 3
		2K 4 4 3 3
		3K 4 4 3 3
		4K 4 4 3 3
		6K 4 4 3 3
		8K 4 4 3 3
		12K 4 4 3 3
		16K 4 18 3 3
		24K 13 17 3 3
		32K 18 18 6 11
		l2/l2 48K 23 20 9 14
		64K 22 23 11 14
		96K 23 23 13 14
		128K 23 23 14 15
		192K 23 23 15 17
		256K 23 23 17 17
		384K 23 24 29 17
		512K 23 24 59 39
		l2/Mem 768K 23 24 86 97
		1M 23 24 112 110
		1.5M 35 25 153 147
		2M 81 56 165 172
		Mem/Mem 3M 167 162 170 179
		4M 217 213 171 182
		6M 251 247 171 182
		8M 260 257 171 182
		12M 263 261 171 182
		16M 265 261 171 182

		Reported-by: Anastasiia Butko <abutko@lbl.gov>

Diff:

Revision 7 (+384 -10)

Show changes

	configs/common/CpuConfig.py
	configs/common/ex5_LITTLE.py
	configs/common/ex5_big.py
	configs/example/arm/fs_bigLITTLE.py

IMO, we don't need the results in the commit message. Unless others disagree it would be good to remove it (no need to repost, though).

Description:

		Changeset 11687:b3946ea8b081
		---------------------------
		arm, config: added support for ex5 model of big.LITTLE

		This patch enables using calibrated big and LITTLE
		cores, ex5_big and ex5_LITTLE instead of the default
		'arm_detailed' and 'minor' cpus. The ex5 model is based
		on the Samsung Exynos 5 Octa (5422) SoC. Operation and
		memory hierarchy latencies have been calibrated using the
		lmbench micro-benchmark suite. The preliminary validation
		results have been published as:
		'Full-System Simulation of big.LITTLE Multicore Architecture
		for Performance and Energy Exploration', in International
		Symposium on Embedded Multicore/Many-core Systems-on-Chip
		(MCSoC'16), Lyon, France (Sep, 2016).

-		lat_ops bench results:
-		----------------------------------------------
-		big LITTLE
-		ops SoC gem5 SoC gem5
-		----------------------------------------------
-		integer bit: 0.5 0.48 0.72 0.7
-		integer add: 0.5 0.55 0.72 0.4
-		integer mul: 1.56 1.68 2.16 1.87
-		integer div: 45.36 36.32 53.3 47.32
-		integer mod: 6.56 18.55 17.37 18.02
-		int64 bit: 0.51 0.98 1.45 1.42
-		uint64 add: 0.63 0.98 1.56 0.93
-		int64 mul: 2.52 2.13 3.64 4.68
-		int64 div: 92.61 195.52 213.14 197.63
-		int64 mod: 47.91 146.78 135.41 138.91
-		float add: 2.52 2.71 2.88 2.61
-		float mul: 3.02 2.84 2.88 2.73
-		float div: 9.07 8.94 12.98 2.82
-		double add: 2.52 2.71 2.88 2.61
-		double mul: 3.02 2.84 5.04 2.73
-		double div: 16.13 10.43 23.03 2.81
-
-		lat_mem_rd bench results:
-		----------------------------------------------
-		big LITTLE
-		cache mem SoC gem5 SoC gem5
-		----------------------------------------------
-		l1/l1 0.5K 4 4 3 3
-		1K 4 4 3 3
-		2K 4 4 3 3
-		3K 4 4 3 3
-		4K 4 4 3 3
-		6K 4 4 3 3
-		8K 4 4 3 3
-		12K 4 4 3 3
-		16K 4 18 3 3
-		24K 13 17 3 3
-		32K 18 18 6 11
-		l2/l2 48K 23 20 9 14
-		64K 22 23 11 14
-		96K 23 23 13 14
-		128K 23 23 14 15
-		192K 23 23 15 17
-		256K 23 23 17 17
-		384K 23 24 29 17
-		512K 23 24 59 39
-		l2/Mem 768K 23 24 86 97
-		1M 23 24 112 110
-		1.5M 35 25 153 147
-		2M 81 56 165 172
-		Mem/Mem 3M 167 162 170 179
-		4M 217 213 171 182
-		6M 251 247 171 182
-		8M 260 257 171 182
-		12M 263 261 171 182
-		16M 265 261 171 182
-
		Reported-by: Anastasiia Butko <abutko@lbl.gov>

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