arch: added generic vector register

Information
Submitter:	Rekai Gonzalez Alberquilla
Repository:	gem5
Branch:	default
Bugs:
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Description

Changeset 11762:0960da820594
---------------------------
arch: added generic vector register

This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.

Nathanael's idea, Rekai's implementation.

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

Testing Done

Builtin regressions

Description:

~		Changeset 11762:51e68b2eed8a
	~	Changeset 11762:8b0fdbea39bf

		arch: added generic vector register

		This commit adds a new generic vector register to have a cleaner
		implementation of SIMD ISAs.

		Nathanael's idea, Rekai's implementation.

		Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
		Reviewed-by: Andreas Sandberg andreas.sandberg@arm.com

Diff:

Revision 2 (+539)

Show changes

src/arch/generic/vec_reg.hh

Seems OK to me. Don't let anyone ever tell you that C++ makes reading code easy... I appreciate all of the compile-time tricks going on here, but it is incredibly difficult to read.
Maybe some more comments for each class that have an example on how to use it would be helpful? I'm a little concerned what's going to happen to this code in 5 years. Will a new person be able to come in and understand what's going on? Though, it isn't like any of this ISA code is understandable until you put weeks or months of effort in. So, feel free to ignore this comment.

Rekai Gonzalez Alberquilla Jan. 24, 2017, 1:52 a.m. (Jan. 24, 2017, 1:52 a.m.)

I will make sure the documentation is more comprehensive. Thanks for taking the time!

LGTM, nice implementation. I just have an ask for a few more comments.

1) A high-level description of the API, and some direction on usage for this library would be useful as a top-level comment in the file.
2) LaneData view is lacking any comments.
3) How should users handle vector operations, e.g. multiplication? Should everything be handled through the views such that the primitive data types are accessed and normal operators used? Or should operators be overloaded here?

Rekai Gonzalez Alberquilla Jan. 24, 2017, 1:58 a.m. (Jan. 24, 2017, 1:58 a.m.)

I will make sure the documentation is more comprehensive.

In the particular for 3), the designer inside me tells me that the proposed class should be just the container for the bits, and provide facilities to access bits, or parts of them, and it is up to the ISA to give semantics to that. Therefore, operators should not be overloaded, and it is up to the ISA side to use the data apropriately. By this I mean, the VecReg should understand things like "Think of the bits as a vector of 32bit elements, and give me the 3rd", but it should be agnostic of whether those bits are a signed int, an unsigned int, a float or any other thing.
Thanks for taking the time!

Tony Gutierrez Jan. 24, 2017, 8:18 a.m. (Jan. 24, 2017, 8:18 a.m.)
```
Makes sense. Thanks.
```

Description:

~		Changeset 11762:8b0fdbea39bf
	~	Changeset 11762:0960da820594

		arch: added generic vector register

		This commit adds a new generic vector register to have a cleaner
		implementation of SIMD ISAs.

		Nathanael's idea, Rekai's implementation.

		Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
		Reviewed-by: Andreas Sandberg andreas.sandberg@arm.com