| ~ | | Changeset 11763:24d2fb13df4d |
| | ~ | Changeset 11839:2ccbe7a4d89d |
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| ~ | | cpu: Added interface for vector reg file |
| | ~ | arch: ISA parser additions of vector registers |
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| ~ | | This patch adds some more functionality to the cpu model and the arch to
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| ~ | | interface with the vector register file. |
| | ~ | Reiley's update :) of the isa parser definitions. My addition of the
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| | ~ | vector element operand concept for the ISA parser. Nathanael's modification
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| | + | creating a hierarchy between vector registers and its constituencies to the
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| | + | isa parser. |
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| ~ | | This change consist mainly in augmenting ThreadContexts and
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| ~ | | ExecContexts with calls to get/set full vectors, underlying
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| ~ | | microarchitectural elements or lanes. Those are meant to interface with
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| | ~ | Some fixes/updates on top to consider instructions as vectors instead of
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| | ~ | floating when they use the VectorRF. Some counters added to all the
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| | ~ | models to keep faithful counts. |
| - | | the vector register file. All classes that implement this interface also
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| - | | get an appropriate implementation. |
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| ~ | | This requires implementing the vector register file for the different
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| | ~ | Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
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| - | | models using the VecRegContainer class. |
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| - | | This change set also updates the Result abstraction to contemplate the
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| - | | possibility of having a vector as result. |
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| - | | The changes also affect how the remote_gdb connection works. |
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| - | | There are some (nasty) side effects, as the need to define dummy values
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| - | | for architectures that do not implement vector extensions.
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| - | | Initialisation of numPysVecRegs in the test configurations, |
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| - | | Nathanael Premillieu's work with an increasing number of fixes and
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| - | | improvements of mine. |
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| - | | Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
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| | | Reviewed-by: Andreas Sandberg andreas.sandberg@arm.com |
