mem: Update DRAM configuration names
Review Request #3783 - Created Jan. 17, 2017 and submitted
| Information | |
|---|---|
| Curtis Dunham | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
| myzinsky | |
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both
the channel and device data width.Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device widthTotal channel width can be calculated by n*w
Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4Updated scripts to match new naming convention.
Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
For me it looks nice:
it addresses an issue that I raised before because there was only one DDR4 x16 Device with 8 banks.
Now we have also x8 and x4 with 16 banks.
Ship It!
While you're on this code, I have a question. Maybe Andreas H. can answer too. Why are all of the configurations for the memory controllers in src/mem/DRAMCtrl.py? They could all be in configs/dram_ctrls/*.py, right? It seems to me that the DRAMCtrl.py file is getting a little out of hand. Is there any reason not to move all of the specific DRAM controller timing definitions to new files in the config/ directory?