SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.
Review Request #431 - Created Jan. 18, 2011 and submitted
| Information | |
|---|---|
| Ali Saidi | |
| gem5 | |
| Reviewers | |
| Default | |
| ali, gblack, nate, stever | |
SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs.
Posted (Jan. 18, 2011, 6:45 p.m.)
I still don't understand how the CPU ends up in a bad state. Could you please list step by step how it happens? Use little words and go slowly :-).
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src/cpu/simple/timing.hh (Diff revision 1) -
It's interesting that we already had an ITBWaitResponse state defined but had never used it before. Does it make sense to add an assert somewhere so that it's not a write-only state? That's just a random comment, not a deficiency in this patch.