Review Board 2.0.15


X86: ISA bug fixes identified when bringing up Barrelfish OS

Review Request #467 - Created Feb. 3, 2011 and submitted

Information
Tim Harris
gem5
Reviewers
Default
ali, gblack, nate, stever
X86: ISA bug fixes identified when bringing up Barrelfish
on M5.  (#1) During iret access LDT/GDT at CPL0 rather than
after transition to user mode (if I'm reading the Intel IA-64 
architecture spec correctly, the contents of the descriptor
table are read before the CPL is updated).  (#2) During 
JMP_FAR_I, use srl to extract the segment selector from the 
top of the destination. (#3) Switch use of t1 and t2 inputs
in jmpFarWork (which was inconsistent with call from JMP_FAR_I)
(#4) During SYSCALL_64, use dataSize=8 when handling new rip
(ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8
IA32_LSTAR is a 64-bit address), (#5) If cr0.wp ("write protect" 
bit) is clear then do not generate page faults when writing to 
write-protected pages in kernel mode.

I'm not sure I've got the correct fix for #3.  I see there are
other calls into jmpFarWork from JMP_FAR_M&P.  I'm not sure
I understand what these are doing, so I'm worried that I've
either missed consequential changes to the use of t1/t2 
somewhere (or that the correct fix is to modify JMP_FAR_I
rather tahn jmpFarWork).

   
Review request changed
Updated (Feb. 6, 2011, 7:27 p.m.)