sparc: compilation fixes for inorder
Review Request #583 - Created March 14, 2011 and submitted
| Information | |
|---|---|
| Korey Sewell | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
| ali, gblack, nate, stever | |
sparc: compilation fixes for inorder Add a few constants and functions that the InOrder model wants for SPARC. * * * sparc: add eaComp function InOrder separates the address generation from the actual access so give Sparc that functionality * * * sparc: add control flags for branches branch predictors and other cpu model functions need to know specific information about branches, so add the necessary flags here
Review request changed
Updated (March 14, 2011, 10:39 a.m.)
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Diff: |
Revision 2 (+134 -4) |
Posted (March 16, 2011, 8:17 a.m.)
There are a number of style issues to clean up, but otherwise this seems mostly ok. I'm still not crazy about having an mt.hh that's only used in InOrder and MIPS, as far as I'm aware. That's ISA specific behavior masquerading as something generic, but that's probably a separate issue from this change.
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src/arch/sparc/isa/decoder.isa (Diff revision 2) -
Needs a space between the comma and None. Should this be marked as IsUncondControl as well?
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src/arch/sparc/isa/formats/mem/basicmem.isa (Diff revision 2) -
You shouldn't add this. This isn't really a C++ file anyway.
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src/arch/sparc/isa/formats/mem/swap.isa (Diff revision 2) -
This line is too long. It needs to be split up. Better yet, exec_output should be appended before the return.
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src/arch/sparc/isa/formats/mem/util.isa (Diff revision 2) -
Checking for faults here (for SPARC at least) isn't necessary as far as I remember.
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src/arch/sparc/isa/formats/mem/util.isa (Diff revision 2) -
Checking for a fault here is probably also unnecessary.
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src/arch/sparc/mt.hh (Diff revision 2) -
Some of these header files don't need to be included.
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src/arch/sparc/mt.hh (Diff revision 2) -
Never put "using namespace" in a header file.
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src/arch/sparc/mt.hh (Diff revision 2) -
This isn't really a user configuration problem since there's no way to even request multithreaded behavior like this in SPARC. I think these should be panics.
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src/arch/sparc/registers.hh (Diff revision 2) -
This seems redundant. Can't the CPU model add them up just as easily?
