ARM: Fix table walk going on while ASID changes error

Information
Submitter:	Ali Saidi
Repository:	gem5
Branch:
Bugs:
Depends On:
Reviewers
Groups:	Default
People:	ali, gblack, nate, stever

Description

ARM: Fix table walk going on while ASID changes error

Testing Done

src/arch/arm/faults.cc (Diff revision 1)

The "Faults" trace flag can be useful during boot to see where things go haywire since early on there shouldn't be any, at least in ISAs with hardware TLB miss handlers. Perhaps you should make this and any other artificial faults use FaultsVerbose or similar so they get ignored unless you really wanted to see them.

Ali Saidi March 30, 2011, 4:47 a.m. (March 30, 2011, 4:47 a.m.)

It's extraordinarily rare that this occurs. The number of things that have to occur are numerous. You have to be running with O3, execute a branch instruction, predict the branch as taken, that prediction has to have an entry in the BTB, the BTB entry has to miss in the TLB, a table walk has to occur to satisfy the miss, and MISCREG_CONTEXIDR has to be written while all this happens. At boot this is never going to happen because the context isn't going to change. I'm inclined to leave it as is.

Gabe Black March 30, 2011, 5:47 a.m. (March 30, 2011, 5:47 a.m.)
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That's fair. Go ahead then.
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src/arch/arm/table_walker.cc (Diff revision 1)

It's not part of this change, but the brackets are messed up on this line.

src/arch/arm/table_walker.cc (Diff revision 1)

This panic doesn't do anything any more.

Ali Saidi March 30, 2011, 4:44 a.m. (March 30, 2011, 4:44 a.m.)
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it does still catch some cases.
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Gabe Black March 30, 2011, 5:46 a.m. (March 30, 2011, 5:46 a.m.)
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Oh, yeah. Duh :-P.
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