Enabled instruction fetch pipelining.
Review Request #718 - Created May 24, 2011 and discarded
| Information | |
|---|---|
| Lisa Hsu | |
| gem5 | |
| Reviewers | |
| Default | |
| ali, gblack, nate, stever | |
Enabled instruction fetch pipelining. This patch is from one of our co-ops who has since finished her term, Yasuko Watanabe. I don't personally know much about it. In the end, I'll push in her name. Thanks.
Posted (May 24, 2011, 3:58 p.m.)
Have you run the regressions for the various ISAs with this patch? Have you tried the applicable ISAs with fetch pipelines deeper than the default (one stage?). The fetch code is subjected to a lot of corner cases and would likely be easy to break in subtle ways, so we need to be really careful. Also, have you considered making this an external component to the CPU? O3 is already very complicated, so if it could make sense to compartmentalize this as another component that would help.
Posted (May 27, 2011, 9:54 a.m.)
I think this type of change is necessary for reasonable performance, but the implementation here does pose some issues for any ISA that uses micro-coded instructions (and faults on one). Additionally, if you look at small issue width CPUs this doesn't generally solve the problem. We've re-worked this change to fix the correctness issue and as soon as it goes through a battery of internal tests we can post it for review if that works for everyone.