Review Board 2.0.15


mips: linked load instruction problem

Review Request #755 - Created June 21, 2011 and updated - Latest diff uploaded

Information
Deyuan Guo
gem5
Reviewers
Default
ali, gblack, nate, stever
The read/setMiscRegNoEffect are declared in inorder_dyn_inst.hh, but not defined in inorder_dyn_inst.cc.
I hope the definitions can be added for the future use.
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The problem is caused by a MIPS linked load instruction. It make the CP0 halt then restart. After that, the tick becomes a large number and it says 'because simulate() limit reached'.

Korey Sewell told me:
    If you get "simulate() reached", that means your system likely deadlocked as there are no more events on the main event queue. Run w/the cpu progress interval on to help determine where the CPUs stops committing instructions. Also, post the locked_mem.hh patch if you want comments on what you are trying to do to resolve the problem.

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I change the locked_mem.hh to an old stable version, to avoid the problem mentioned above. But I know this is not 'fixing the bug', but 'avoiding the bug'.
Only single thread.