LSQ: Only trigger a memory  violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dependency
checking).

The performance improvement on SPEC benchmarks can be substantial (2-10%).

This patch has been tested with a couple of self-checking hand crafted programs I wrote to stress ordering between two cores. With injected bugs it definitely shows a failure and it doesn't with this implementation (and it caught one issue during development).