Big squashed diff of changes that merge SE and FS modes.
Review Request #928 - Created Dec. 8, 2011 and submitted
| Information | |
|---|---|
| Gabe Black | |
| gem5 | |
| Reviewers | |
| Default | |
| gblack | |
This is a squashed diff of my merged repository and the main repository. I created it by merging the two in my repository and running this command: hg diff -r 7ee2e35da276 -r 669e93d79ed9 --git > sefsmergesquashed.patch
Ran all regressions for all ISAs and one RUBY specific ALPHA configuration.
It's nice to see this getting close to done... Did you verify there were no stats changes at all? One of my biggest issues with it is the extra indenting that is used a lot of places to do something like:
func()
{
if (FullSystem) {
....
....
....
....
....
....
....
....
}
}
and I'd much rather see:
func()
{
if (!FullSystem)
return;
....
....
}
-
configs/common/Simulation.py (Diff revision 1) -
Is there any issue with setting workload on a CPU that is running in full system mode?
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src/arch/alpha/AlphaSystem.py (Diff revision 1) -
Why is there a blank line here?
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src/arch/alpha/faults.cc (Diff revision 1) -
I'm not crazy about replacing #if with if () and all the indenting that goes with it. Could we maybe structure these things like if (FullSystem) return .... ....?
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src/arch/alpha/isa/fp.isa (Diff revision 1) -
Doesn't seem like FullSystem si needed here either as long as we initialize the ICSR register to have FP enabled for non-fullsystem mode
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src/arch/alpha/tlb.cc (Diff revision 1) -
I imagine this would be one of those high-performance areas. It's probably not necessary to have the check here either. As long as PcPAL exists (i think it just checks if the PC is odd).
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src/arch/alpha/utility.cc (Diff revision 1) -
Here too can we structure there like: if (!FullSystem) panic("getArgument()...") ... the dummy return can go away. -
src/arch/arm/tlb.cc (Diff revision 1) -
How is this code ever called this this is translateSe? It's already handled with the indirection between translateSe and translateFs
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src/arch/arm/tlb.cc (Diff revision 1) -
This is definitely in the critical path. as long as bootUncachability is initialized to true in SE mode this extra check isn't needed. Also this should already be handled by the indirection between translateSe and translateFs below
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src/arch/arm/tlb.cc (Diff revision 1) -
very much in the critical path.
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src/arch/power/tlb.cc (Diff revision 1) -
less indent please
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src/arch/power/vtophys.cc (Diff revision 1) -
is it posible to have this many authors and copyright holders on what is pretty much a null file?
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src/arch/sparc/faults.cc (Diff revision 1) -
return SparcFaultBase::invoke(tc, inst);
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src/arch/sparc/isa/base.isa (Diff revision 1) -
Same?
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src/arch/sparc/tlb.cc (Diff revision 1) -
Seems like the se version should just get the data from the tag access register instead of having a different fault defined
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src/arch/sparc/tlb.cc (Diff revision 1) -
same I think now is the only time I imagine this would get cleaned up, so that is why I'm asking
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src/arch/sparc/utility.cc (Diff revision 1) -
Move the panic to the top and then have the rest of the code unidented?
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src/arch/x86/faults.cc (Diff revision 1) -
Same
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src/dev/alpha/backdoor.cc (Diff revision 1) -
seems like a random change?
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src/dev/alpha/backdoor.cc (Diff revision 1) -
probably should be a fatal as it's not performance critical and would cause a segfault if it didn't cast
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src/sim/pseudo_inst.cc (Diff revision 1) -
if (!FullSystem) panic()
Change Summary:
Update testing now that I've run all the regressions. Also take out the part about excluding the testing directory since I'm not any more.
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Testing Done: |
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Change Summary:
Merge with more recent version of the head, and implement Ali's review feedback.
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Diff: |
Revision 3 (+2163 -3271) |
It certainly is a great big diff. It looks fine to me, thanks for addressing my comments. I might have something minor, but I'd rather get it committed now and fix that later.
