MEM: Add the system port as a central access point

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Submitter:	Andreas Hansson
Repository:	gem5
Branch:	default
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Description

MEM: Add the system port as a central access point

The system port is used as a globally reachable access point to the
memory subsystem. The benefit of using an actual port is that the
usual infrastructure is used to resolve any access and thus makes the
overall system able to handle distributed memories in any
configuration, and also makes the accesses agnostic to the address
map. This patch only introduces the port and does not actually use it
for anything.

Testing Done

util/regress all passing (disregarding t1000 and eio)

Why do you need setParent()? You could make every simobject have a parameter called System and have the default value be Parent.any (see src/dev/Device.py).

Andreas Hansson Jan. 3, 2012, 11:09 p.m. (Jan. 3, 2012, 11:09 p.m.)

After attempting a "simple" implementation as suggested, with one line in SimObject.py my conclusion is that it is more complicated than what it seems. Conceptually it is a good idea (there is no inherent reason why the whole setParent() is needed), but I struggle to get Python to appreciate the Param and Parent objects. Do you have any suggestions on how to do this?

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Revision 2 (+56 -4)

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	src/sim/System.py
	src/sim/system.hh
	src/sim/system.cc

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Revision 3 (+58 -4)

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	src/sim/System.py
	src/sim/system.hh
	src/sim/system.cc

great!

src/sim/system.hh (Diff revision 3)

Do we need a special function for this, as opposed to other objects just calling getPort("system_port")?

Andreas Hansson Jan. 10, 2012, 6:05 p.m. (Jan. 10, 2012, 6:05 p.m.)

I want to get away from using getPort(const std::string&) in the C++ code all together as the "magic" names like system_port, icache_port, dcache_port etc refer to persistent and very specific ports that the objects would not be complete without. Thus, for the few objects where we get pointers to ports in the C++ code I eventually want to end up with similar functions like getDataPort() and getInstPort() on a CPU. If a port name changes that is then limited to the Python "assembly" scripts and the mapping of those names to port pointers when connecting them up.

Good answer...

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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