CPU: Moving towards a more general port across CPU models
Review Request #944 - Created Dec. 18, 2011 and submitted
| Information | |
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| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system.
util/regress all passing (disregarding t1000 and eio)
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src/cpu/base.hh (Diff revision 2) -
Aren't these virtual as well?
Posted (Jan. 3, 2012, 5:49 p.m.)
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src/cpu/base.hh (Diff revision 2) -
At the moment there is no need to do anything for any of the CPU models when receiving a status change (they simply have no choice when it comes to address ranges anyhow). They should also never receive any functional accesses since they are master ports (and functional requests return without any backwards path). When we eventually add a snooping port for the LSQ (for ARM but potentially also others) that port will behave in a different way.
In isolation this looks like a wash... the code is pretty similar but just moved around. I don't see anything wrong with it though. I'll take your word that it's a useful step toward better things.