MEM: Removing the default port peer from Python ports
Review Request #952 - Created Dec. 22, 2011 and submitted
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
MEM: Removing the default port peer from Python ports In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.
util/regress all passing (disregarding t1000 and eio)
Posted (Jan. 10, 2012, 12:03 p.m.)
Interesting... my initial reaction was to object that it seemed like overkill to get rid of the default option entirely, but since it was only used it two places, it's hard to justify keeping it in there. You should also delete these two lines of MetaSimObject._new_port() which are what make Port defaults actually work: http://repo.gem5.org/gem5/file/f72bbe6b13fb/src/python/m5/SimObject.py#l276