MEM: Differentiate functional cache accesses from CPU and memory
Review Request #979 - Created Jan. 4, 2012 and submitted
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
MEM: Differentiate functional cache accesses from CPU and memory This patch changes the functionalAccess member function in the cache model such that it is aware of what port the access came from, i.e. if it came from the CPU side or from the memory side. By adding this information, it is possible to respect the 'forwardSnoops' flag for snooping requests coming from the memory side and not forward them. This fixes an outstanding issue with the IO bus getting accesses that have no valid destination port and also cleans up future changes to the bus model.
util/regress all passing (disregarding t1000 and eio)
Review request changed
Updated (Jan. 10, 2012, 1:16 a.m.)
Diff: |
Revision 2 (+16 -11) |
|---|
looks great
Posted (Jan. 10, 2012, 2:02 p.m.)
Maybe the old code was trying too hard to be clever, but this seems like a bigger change than necessary. Why not just add the fromCpuSide flag like you've done, but without getting rid of incomingPort and otherSidePort, and then the only thing you'd have to change in functionalAccess() is this:
if (done) {
pkt->makeResponse();
} else {
otherSidePort->sendFunctional(pkt);
}
to this:
if (done) {
pkt->makeResponse();
} else if (fromCpuSide || forwardSnoops) {
otherSidePort->sendFunctional(pkt);
}