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[Submitted] config: Add a check for fastmem only used with Atomic CPU
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ahansson
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October 25th, 2012, 10:35 a.m.
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[Submitted] config: Remove unused mem_size in fs.py
|
ahansson
|
October 25th, 2012, 10:35 a.m.
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[Submitted] sim: Add drain methods to request additional cleanup operations
|
ali
|
October 24th, 2012, 3:07 p.m.
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[Submitted] ARM: Make ID registers ISA parameters
|
ali
|
October 24th, 2012, 3:05 p.m.
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[Submitted] arch: Make the ISA class inherit from SimObject
|
ali
|
October 24th, 2012, 3:04 p.m.
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[Submitted] sim: Add SWIG interface for Serializable
|
ali
|
October 24th, 2012, 3:03 p.m.
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[Submitted] python: Rename doDrain()->drain() and make it do the right thing
|
ali
|
October 24th, 2012, 2:52 p.m.
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[Submitted] sim: Reuse the code to change memory mode.
|
ali
|
October 24th, 2012, 2:33 p.m.
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[Submitted] sim: Move the draining interface into a separate base class
|
ali
|
October 24th, 2012, 2:32 p.m.
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[Submitted] cpu: O3 add a header declaring the DerivO3CPU
|
ali
|
October 24th, 2012, 2:28 p.m.
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[Submitted] cpu: Add header files for checker CPUs
|
ali
|
October 24th, 2012, 2:27 p.m.
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[Submitted] dev: Fix ethernet device inheritance structure
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] sim: Include object header files in SWIG interfaces
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] pci: Make Python wrapper cast to the right type
|
ali
|
October 24th, 2012, 2:23 p.m.
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[Submitted] mips: Remove unused Python file
|
ali
|
October 24th, 2012, 2:23 p.m.
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[Submitted] dev: Add missing inline declarations
|
ali
|
October 24th, 2012, 2:22 p.m.
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[Submitted] base: Add missing header file to addr_range.hh.
|
ali
|
October 24th, 2012, 2:22 p.m.
|
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[Submitted] m5: Expose m5 pseudo-instructions to C/C++ via a static library
|
ali
|
October 24th, 2012, 2:21 p.m.
|
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[Submitted] base: Fix a few incorrectly handled print format cases
|
ali
|
October 24th, 2012, 2:20 p.m.
|
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[Submitted] base: split out the VncServer into a VncInput and Server classes
|
ali
|
October 24th, 2012, 2:19 p.m.
|
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[Submitted] ISA: generic Linux thread info support
|
ali
|
October 24th, 2012, 2:19 p.m.
|
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[Submitted] sim: Fix as issue where exit events on instr queues are used after freed.
|
ali
|
October 24th, 2012, 2:19 p.m.
|
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[Submitted] o3: Fix a couple of issues with the local predictor.
|
ali
|
October 24th, 2012, 2:18 p.m.
|
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[Submitted] Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
|
ali
|
October 24th, 2012, 2:18 p.m.
|
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[Submitted] ruby: add support for prefetching to MESI protocol
|
nilay
|
October 24th, 2012, 12:39 p.m.
|
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[Submitted] ruby: modify the directed tester to read/write streams
|
nilay
|
October 24th, 2012, 12:39 p.m.
|
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[Submitted] ruby: change slicc to allow for constructor args
|
nilay
|
October 24th, 2012, 12:38 p.m.
|
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[Submitted] ruby: add a prefetcher
|
nilay
|
October 24th, 2012, 12:37 p.m.
|
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[Submitted] ruby: add functions for computing next stride/page address
|
nilay
|
October 24th, 2012, 12:37 p.m.
|
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[Submitted] ruby: bug in functionalRead, revert recent changes
|
nilay
|
October 24th, 2012, 12:36 p.m.
|
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[Submitted] ruby: support functional accesses in garnet flexible network
|
nilay
|
October 24th, 2012, 12:35 p.m.
|
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[Submitted] Ruby Config: Add Argument for marking caches as Inst Only - MESI/MOESI
|
musleh
|
October 24th, 2012, 8:18 a.m.
|
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[Submitted] config: Use shared cache config for regressions
|
ahansson
|
October 24th, 2012, 7:13 a.m.
|
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|
O3: Show per-stage aggregate statistics detailing the reasons for block/stall cycles
|
vilanova
|
October 23rd, 2012, 11:38 a.m.
|
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|
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[Submitted] Add command/pseudo-instruction m5fail
|
vilanova
|
October 23rd, 2012, 11:33 a.m.
|
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[Submitted] X86: Generate code for 'm5_writefile'
|
vilanova
|
October 23rd, 2012, 11:27 a.m.
|
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[Submitted] dev: Make default clock more reasonable for system and devices
|
ahansson
|
October 23rd, 2012, 2:28 a.m.
|
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[Submitted] arm: Use table walker clock that is inherited from CPU
|
ahansson
|
October 23rd, 2012, 2:25 a.m.
|
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[Submitted] config: Use SimpleDRAM in full-system, and with o3 and inorder
|
ahansson
|
October 20th, 2012, 8:44 a.m.
|
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[Discarded] gem5: Add the ability to create SimPoint BBV profiles
|
mhayenga
|
October 19th, 2012, 3:03 p.m.
|
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[Discarded] gem5: Add the ability to create SimPoint BBV profiles
|
mhayenga
|
October 19th, 2012, 2:46 p.m.
|
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[Submitted] dev: Remove zero-time loop in DMA timing send
|
ahansson
|
October 19th, 2012, 2:29 a.m.
|
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[Submitted] cache: remove drainManager because it's not used
|
atgutier
|
October 16th, 2012, 9:47 a.m.
|
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[Submitted] Checkpoint: Make system serialize call children
|
ahansson
|
October 12th, 2012, 1:46 a.m.
|
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|
[Submitted] Mem: Use deque instead of list for bus retries
|
ahansson
|
October 12th, 2012, 1:41 a.m.
|
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[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
|
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|
|
[Submitted] Ruby: Add Ruby Stats Hit/Miss Profile Access for Protocols
|
musleh
|
October 7th, 2012, 4:59 p.m.
|
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|
|
[Discarded] Ruby: Add Ruby Stats Hit/Miss Profile Access for MESI/MOESI Protocols
|
musleh
|
October 7th, 2012, 12:58 p.m.
|
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|
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[Submitted] ARM: Set "uopSet_uop" as Conditional or Unconditional control
|
npremill
|
October 6th, 2012, 3:35 p.m.
|
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|
|
[Submitted] patch to fix early termination in SE multi-core simualtion
|
taozhang
|
October 5th, 2012, 3:45 p.m.
|
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