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[Submitted] SWIG: Make gem5 compile and link with swig 2.0.4
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ahansson
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December 19th, 2011, 5:51 a.m.
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[Submitted] MEM: Prepare mport for master/slave split
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ahansson
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February 20th, 2012, 2:55 a.m.
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[Submitted] mem: Add explicit Cache subclass and make BaseCache abstract
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ahansson
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August 13th, 2015, 8:31 p.m.
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[Submitted] mem: Enforce insertion order on the cache response path
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ahansson
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October 13th, 2015, 3:36 p.m.
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[Submitted] base: Add wrapped protobuf input stream
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ahansson
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December 6th, 2012, 7:53 p.m.
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stats: Add length of all stats to the SQL stats table
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ahansson
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January 15th, 2013, 10:33 a.m.
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[Submitted] mem: More descriptive enum names for address mapping
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ahansson
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March 28th, 2013, 3:28 a.m.
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[Submitted] cpu: Block traffic generator when requests have to retry
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ahansson
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April 23rd, 2013, 12:29 a.m.
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[Submitted] mem: Remove the cache builder
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ahansson
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May 23rd, 2013, 12:44 a.m.
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[Discarded] scons: Move the warning about self assignment to SWIG code only
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ahansson
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June 28th, 2013, 10:34 a.m.
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[Submitted] alpha: Move system virtProxy to Alpha only
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ahansson
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August 19th, 2013, 9:34 a.m.
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[Submitted] mem: Use the same timing calculation for DRAM read and write
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ahansson
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October 16th, 2013, 7:40 a.m.
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[Submitted] arch, arm: Preserve TLB bootUncacheability when switching CPUs
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ahansson
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April 23rd, 2014, 12:22 p.m.
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[Submitted] scons: Warn for incompatible gcc and binutils
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ahansson
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July 28th, 2014, 5:50 a.m.
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[Submitted] dev: Add a VirtIO console device model
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ahansson
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September 10th, 2014, 7:52 a.m.
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[Submitted] arch: Use shared_ptr for all Faults
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ahansson
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September 29th, 2014, 10:40 a.m.
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[Submitted] mem: Add a GDDR5 DRAM config
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ahansson
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November 17th, 2014, 6:13 a.m.
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[Submitted] x86: Delay X86 table walk on receiving walker response
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ahansson
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January 5th, 2015, 4:35 p.m.
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[Submitted] arm: Wire up the GIC with the platform in the base class
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ahansson
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February 5th, 2015, 10:59 a.m.
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[Submitted] mem: Add byte mask to Packet::checkFunctional
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ahansson
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February 19th, 2015, 7:56 a.m.
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[Submitted] mem: Remove redundant allocateUncachedReadBuffer in cache
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ahansson
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March 17th, 2015, 7:09 p.m.
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[Submitted] Atomic: Remove the physmem_port and access memory directly
|
ahansson
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March 20th, 2012, 10:30 a.m.
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[Submitted] MEM: Use base class Master/SlavePort pointers in the bus
|
ahansson
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April 9th, 2012, 9:40 a.m.
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[Submitted] mem: Make the coherent crossbar account for timing snoops
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ahansson
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August 19th, 2015, 9:06 a.m.
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[Submitted] mem: Do not treat CleanEvict as a write operation
|
ahansson
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October 30th, 2015, 10:33 a.m.
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[Submitted] arm: Use table walker clock that is inherited from CPU
|
ahansson
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October 23rd, 2012, 2:25 a.m.
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[Submitted] mem: Add DDR3 and LPDDR2 DRAM controller configurations
|
ahansson
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December 6th, 2012, 8:31 p.m.
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[Submitted] config: Break out base options for usage with NULL ISA
|
ahansson
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October 20th, 2016, 11:07 a.m.
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[Submitted] mem: Fix CommMonitor style and response check
|
ahansson
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June 4th, 2013, 10:47 a.m.
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[Submitted] cpu: Fix TrafficGen trace playback
|
ahansson
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July 18th, 2013, 1:17 p.m.
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[Submitted] mem: Wakeup sleeping CPUs without caches on LLSC
|
ahansson
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February 21st, 2014, 1:21 p.m.
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[Submitted] mem: Limit the accesses to a page before forcing a precharge
|
ahansson
|
March 7th, 2014, 11:40 p.m.
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[Submitted] scons: Bump the compiler version to gcc 4.6 and clang 3.0
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
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[Submitted] arm: allow DC instructions by default so SE mode works
|
ahansson
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April 23rd, 2014, 12:27 p.m.
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[Submitted] style: Fixup strange semantics in hg m5style
|
ahansson
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August 13th, 2014, 12:51 p.m.
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[Submitted] cpu: Fix o3 quiesce fetch bug
|
ahansson
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August 23rd, 2014, 5:08 a.m.
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[Submitted] mem: Tie in the snoop filter in the coherent bus
|
ahansson
|
September 10th, 2014, 7:53 a.m.
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[Submitted] scons: Add --without-tcmalloc build option
|
ahansson
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September 29th, 2014, 10:37 a.m.
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[Submitted] cpu, o3: Ignored invalidate causing same-address load reordering
|
ahansson
|
November 17th, 2014, 6:18 a.m.
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[Submitted] mem: Add rank-wise refresh to the DRAM controller
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] base: Add XOR-based hashed address interleaving
|
ahansson
|
January 21st, 2015, 1:22 p.m.
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[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
|
ahansson
|
January 18th, 2012, 2:35 a.m.
|
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[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
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[Submitted] MEM: Remove the Broadcast destination from the packet
|
ahansson
|
April 4th, 2012, 12:52 a.m.
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[Submitted] scons: Enable -Wextra by default
|
ahansson
|
December 28th, 2015, 6:14 p.m.
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[Submitted] Device: Bump PIO and PCI latencies to more reasonable values
|
ahansson
|
August 29th, 2012, 3:37 p.m.
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[Submitted] Mem: Add a maximum bandwidth to SimpleMemory
|
ahansson
|
September 12th, 2012, 9:38 a.m.
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[Submitted] configs: Add a lat_mem_rd style test script
|
ahansson
|
February 15th, 2016, 9:01 a.m.
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[Submitted] mem: Tidy up bus addr range debug messages
|
ahansson
|
November 1st, 2012, 1:49 a.m.
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stats: Add example script to extract stats from SQL database
|
ahansson
|
January 15th, 2013, 10:27 a.m.
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