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[Submitted] config: Add --memchecker option
|
ahansson
|
December 12th, 2014, 5:45 p.m.
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[Submitted] mem: Add a stack distance calculator
|
ahansson
|
December 12th, 2014, 5:45 p.m.
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[Submitted] mem: Add stack distance statistics to the CommMonitor
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] mem: Add rank-wise refresh to the DRAM controller
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] mem: Ensure DRAM controller is idle when in atomic mode
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] config: Expose the DRAM ranks as a command-line option
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] arm: Add stats to table walker
|
ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] mem: Add parameter to reserve MSHR entries for demand access
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ahansson
|
December 12th, 2014, 5:46 p.m.
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[Submitted] mem: Rework the structuring of the prefetchers
|
ahansson
|
December 12th, 2014, 5:47 p.m.
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[Submitted] mem: Fix bug relating to writebacks and prefetches
|
ahansson
|
December 12th, 2014, 5:49 p.m.
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[Submitted] mem: Fix event scheduling issue for prefetches
|
ahansson
|
December 12th, 2014, 5:49 p.m.
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[Submitted] mem: Hide WriteInvalidate requests from prefetchers
|
ahansson
|
December 12th, 2014, 5:50 p.m.
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[Submitted] mem: Change prefetcher to use random_mt
|
ahansson
|
December 12th, 2014, 5:50 p.m.
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[Submitted] tests: Remove deprecated InOrderCPU tests
|
ahansson
|
December 18th, 2014, 6:46 p.m.
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[Submitted] scons: Do not build the InOrderCPU
|
ahansson
|
December 19th, 2014, 1:20 p.m.
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[Submitted] mem: Clean up Request initialisation
|
ahansson
|
January 5th, 2015, 4:35 p.m.
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[Submitted] x86: Delay X86 table walk on receiving walker response
|
ahansson
|
January 5th, 2015, 4:35 p.m.
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[Submitted] mem: Make the XBar responsible for tracking response routing
|
ahansson
|
January 5th, 2015, 4:36 p.m.
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[Submitted] mem: Always use SenderState for response routing in RubyPort
|
ahansson
|
January 5th, 2015, 4:50 p.m.
|
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[Submitted] mem: Remove unused RequestState in the bridge
|
ahansson
|
January 5th, 2015, 4:53 p.m.
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[Submitted] mem: Remove Packet source from ForwardResponseRecord
|
ahansson
|
January 12th, 2015, 4:09 p.m.
|
|
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[Submitted] mem: Remove unused Packet src and dest fields
|
ahansson
|
January 12th, 2015, 4:10 p.m.
|
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[Submitted] config: Adjust DRAM channel interleaving defaults
|
ahansson
|
January 21st, 2015, 1:22 p.m.
|
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[Submitted] base: Add XOR-based hashed address interleaving
|
ahansson
|
January 21st, 2015, 1:22 p.m.
|
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[Submitted] config: Add XOR hashing to the DRAM channel interleaving
|
ahansson
|
January 21st, 2015, 1:23 p.m.
|
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[Submitted] cpu: Tidy up the MemTest and make false sharing more obvious
|
ahansson
|
January 21st, 2015, 1:23 p.m.
|
|
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[Submitted] config: Revamp memtest to allow testers on any level
|
ahansson
|
January 21st, 2015, 1:24 p.m.
|
|
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|
[Submitted] style: Update the style checker to handle new include order
|
ahansson
|
January 26th, 2015, 5:55 p.m.
|
|
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[Submitted] mem: Clarify cache behaviour for pending dirty responses
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
|
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|
[Submitted] mem: Clarify express snoop behaviour
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
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[Submitted] cpu: Ensure timing CPU sinks response before sending new request
|
ahansson
|
January 27th, 2015, 10:19 a.m.
|
|
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[Submitted] config: add --root-device machine parameter
|
ahansson
|
January 28th, 2015, 10:06 a.m.
|
|
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|
[Submitted] arch: Make readMiscRegNoEffect const throughout
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
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|
[Submitted] mem: Use the range cache for lookup as well as access
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] mem: mmap the backing store with MAP_NORESERVE
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] mem: Fix initial value problem with MemChecker
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] config: Add memcheck stress test
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
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|
[Submitted] base: Add compiler macros to add deprecation warnings
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
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[Submitted] sim: Move the BaseTLB to src/arch/generic/
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] arm: Wire up the GIC with the platform in the base class
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] style: Fix incorrect style checker option name
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] style: Fix broken m5format command
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] base: Do not dereference NULL in CompoundFlag creation
|
ahansson
|
February 5th, 2015, 11:36 a.m.
|
|
|
|
[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
|
[Submitted] mem: Clarification of packet crossbar timings
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
|
[Submitted] mem: Split port retry for all different packet classes
|
ahansson
|
February 7th, 2015, 5:24 p.m.
|
|
|
|
[Submitted] cpu: o3 register renaming request handling improved
|
ahansson
|
February 7th, 2015, 5:24 p.m.
|
|
|
|
[Submitted] dev: Fix undefined behaviuor in i8254xGBe
|
ahansson
|
February 9th, 2015, 2:24 p.m.
|
|
|
|
[Submitted] mem: Fix prefetchSquash + memInhibitAsserted bug
|
ahansson
|
February 13th, 2015, 8:36 a.m.
|
|
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|
[Submitted] tests: Run regression timeout as foreground
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
