|
|
[Submitted] mem: per-thread cache occupancy and per-block ages
|
ali
|
November 14th, 2013, 9:09 p.m.
|
|
|
|
[Submitted] MEM: Pass the ports from Python to C++ using the Swig params
|
ahansson
|
January 18th, 2012, 2:32 a.m.
|
|
|
|
[Submitted] mem: Pass shared downstream through caches
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] mem: Page Table map api modification
|
alexdutu
|
October 6th, 2014, 6:58 p.m.
|
|
|
|
[Submitted] mem: Page Table long lines
|
alexdutu
|
September 30th, 2014, 7:32 p.m.
|
|
|
|
[Submitted] mem: packet: Add const to constructor argument
|
nilay
|
June 29th, 2015, 6:18 a.m.
|
|
|
|
[Submitted] mem: Order packet queue only on matching addresses
|
ahansson
|
October 13th, 2015, 3:36 p.m.
|
|
|
|
[Submitted] mem: Only track snooping ports in the snoop filter
|
ahansson
|
August 21st, 2015, 3:50 p.m.
|
|
|
|
[Discarded] mem: Only forward the non-writable flag if truly needed
|
ahansson
|
December 9th, 2015, 11:58 p.m.
|
|
|
|
[Submitted] mem: Multi Level Page Table bug fix
|
alexdutu
|
September 30th, 2014, 7:18 p.m.
|
|
|
|
mem: MSHR livelock bug fix
|
atgutier
|
May 11th, 2015, 10:19 p.m.
|
|
|
|
[Submitted] mem: Move trace functionality from the CommMonitor to a probe
|
andysan
|
June 17th, 2015, 6:48 a.m.
|
|
|
|
[Submitted] mem: Move the point of coherency to the coherent crossbar
|
ahansson
|
January 1st, 2016, 2:33 p.m.
|
|
|
|
[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
|
|
|
[Submitted] mem: Move crossbar default latencies to subclasses
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] mem: Move cache_impl.hh to cache.cc
|
ahansson
|
August 13th, 2015, 8:29 p.m.
|
|
|
|
[Submitted] MEM: Move all read/write blob functions from Port to PortProxy
|
ahansson
|
February 15th, 2012, 5:58 a.m.
|
|
|
|
[Submitted] mem: More descriptive enum names for address mapping
|
ahansson
|
March 28th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] mem: More descriptive DRAM config names
|
ahansson
|
May 14th, 2013, 12:45 a.m.
|
|
|
|
[Submitted] mem: More descriptive address-mapping scheme names
|
ahansson
|
March 7th, 2014, 11:35 p.m.
|
|
|
|
[Submitted] mem: Modify drain to ensure banks and power are idled
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Discarded] mem: Modernise the CacheSet class, and avoid templates
|
ahansson
|
August 31st, 2015, 9:20 a.m.
|
|
|
|
[Submitted] mem: Modernise MSHR iterators to C++11
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
mem: model data array bank in classic cache
|
rioshering
|
March 31st, 2013, 3:47 p.m.
|
|
|
|
[Submitted] mem: mmap the backing store with MAP_NORESERVE
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] mem: misc flags for AMD gpu model
|
atgutier
|
October 30th, 2015, 9:52 p.m.
|
|
|
|
[Discarded] mem: minor fixes in the HMC vault model
|
azarkhish
|
July 1st, 2015, 10:25 a.m.
|
|
|
|
[Submitted] mem: Minor dprintf fix to abstract mem
|
atgutier
|
September 27th, 2016, 11 p.m.
|
|
|
|
[Discarded] mem: minor change in the XBar class
|
azarkhish
|
July 1st, 2015, 10:28 a.m.
|
|
|
|
[Submitted] mem: Merge ranges that are part of the conf table
|
ahansson
|
December 6th, 2012, 8:16 p.m.
|
|
|
|
[Discarded] mem: Merge ranges that are part of the conf table
|
ahansson
|
November 1st, 2012, 10:38 a.m.
|
|
|
|
[Submitted] mem: Merge ranges in bus before passing them on
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Merge interleaved ranges when creating backing store
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM latency calculation and bank state update
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Make tXAW enforcement less conservative and per rank
|
ahansson
|
October 16th, 2013, 7:42 a.m.
|
|
|
|
[Submitted] mem: Make the XBar responsible for tracking response routing
|
ahansson
|
January 5th, 2015, 4:36 p.m.
|
|
|
|
[Submitted] mem: Make the XBar responsible for tracking response routing
|
atgutier
|
July 7th, 2014, 9:52 p.m.
|
|
|
|
[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
|
ahansson
|
January 18th, 2012, 2:35 a.m.
|
|
|
|
[Submitted] mem: Make the requests carried by packets const
|
ahansson
|
November 17th, 2014, 6:15 a.m.
|
|
|
|
[Submitted] mem: Make the coherent crossbar account for timing snoops
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] mem: Make the buses multi layered
|
ahansson
|
April 22nd, 2013, 3:35 p.m.
|
|
|
|
[Submitted] MEM: Make the bus default port yet another port
|
ahansson
|
December 23rd, 2011, 1:38 a.m.
|
|
|
|
[Submitted] MEM: Make the bus bridge unidirectional and fixed address range
|
ahansson
|
December 23rd, 2011, 1:32 a.m.
|
|
|
|
[Submitted] Mem: Make SimpleMemory single ported
|
ahansson
|
June 17th, 2012, 10:18 a.m.
|
|
|
|
[Submitted] mem: Make returning snoop responses occupy response layer
|
ahansson
|
April 22nd, 2013, 3:37 p.m.
|
|
|
|
[Submitted] mem: Make Request getters const
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] MEM: Make port proxies use references rather than pointers
|
ahansson
|
February 15th, 2012, 5:56 a.m.
|
|
|
|
[Submitted] mem: Make packet debug printing more uniform
|
nnikoleris
|
November 18th, 2016, 4:42 p.m.
|
|
|
|
[Submitted] mem: Make packet bus-related time accounting relative
|
ahansson
|
February 14th, 2013, 1:52 a.m.
|
|
